Multi-DAC Comparator Testing for Faster Semiconductor IC Screening
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Solution Overview
Problem
Conventional methods for testing semiconductor integrated circuits with multiple digital-to-analog converters (DACs) are inefficient, requiring increased circuit scale and not suitable for pre-shipping pass/fail judgments, as they rely on the premise that multiple DACs do not fail simultaneously and have poor failure detection efficiency.
Innovation Solution
A semiconductor device and testing apparatus that includes a setting unit for digital input values, a comparison unit for analog output values, and an offset correction unit, which allows for a pass/fail judgment by alternately increasing or decreasing digital input values to achieve an expected pattern of alternately inverted output signals, enabling efficient testing of two or more DACs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional comparison methods using three or more DACs are used, then failure detection is possible in operating systems, but the method is not suitable for pre-shipping pass/fail judgment and has poor failure detection efficiency
Solution Approach 1:
The invention segments the testing process by dividing DACs into pairs and testing each pair independently using dedicated comparison units. This segmentation allows parallel testing of multiple DAC pairs simultaneously, significantly improving test speed while maintaining reliable failure detection through systematic pairing and comparison.
Solution Approach 2:
The invention performs preliminary pairing of DACs before the actual comparison test. By pre-organizing DACs into pairs and preparing comparison units in advance, the testing process can proceed efficiently without setup delays during the actual test, improving both speed and reliability.
2Measurement precision
If ADCs higher in precision than DACs are used for testing, then high-resolution DAC testing is enabled, but the circuit scale of the semiconductor integrated circuit is undesirably increased
Solution Approach 1:
The invention uses DAC outputs as reference copies for comparing other DACs. Instead of introducing external high-precision ADCs, the system copies the output signal from one DAC and uses it as a reference for comparison with another DAC through comparison units, maintaining testing precision without increasing circuit scale.
Solution Approach 2:
The invention introduces comparison units as intermediaries between DACs. These comparison units directly compare analog output values from different DACs without requiring high-precision ADCs, serving as a mediator that enables precise DAC testing while avoiding the need for additional high-precision conversion circuits.
3Reliability
If the conventional method repeats comparing odd-numbered and even-numbered DACs successively, then all DACs can be tested, but the failure detection efficiency is poor and test time is increased
Solution Approach 1:
The invention implements periodic action by systematically pairing DACs (first DAC with second DAC, third with fourth, etc.) and performing comparisons in a regular, repeating pattern. This periodic pairing structure ensures all DACs are tested comprehensively while maintaining efficient test throughput through consistent, rhythmic testing cycles.
Solution Approach 2:
The invention merges the testing of multiple DACs into paired comparisons. By combining two DACs into each comparison unit and testing them simultaneously, the system achieves comprehensive coverage of all DACs while reducing the total number of separate test operations needed, thereby decreasing overall test time.
Data Source
AI summary
In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution.When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.