Multi-DAC DDS Circuit With Mixer for Low-Spur Frequency Switching
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Solution Overview
Problem
Existing direct digital synthesizers (DDS) face challenges with noise and spur generation due to high-frequency operation of digital to analog converters (DACs), which are exacerbated by slow frequency switching in phase locked loops (PLL) and limited by sample clock phase noise and reconstruction noise.
Innovation Solution
A DDS circuit employing multiple parallel DACs with synchronized clock signals and a multiplexing switch, combined with a multi-mode mixer, ensures DAC outputs settle before being provided, reducing noise and spurs by using synchronized clock signals and a return-to-zero mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high-speed DAC is used to achieve fast frequency switching, then frequency switching speed is improved, but noise and spurs increase due to incomplete settling
Solution Approach 1:
The patent divides the DAC functionality into multiple parallel DACs (first DAC, second DAC, etc.) that operate on alternating samples. This segmentation allows each DAC to process fewer samples at a time, enabling faster settling while maintaining high overall output frequency. The switch alternates between DAC outputs, effectively doubling the output rate without requiring individual DACs to settle completely for every sample.
Solution Approach 2:
The patent implements periodic switching between multiple DACs using a switch that alternates between first DAC output and second DAC output based on alternating samples. This periodic action allows each DAC to settle during its active period while the other DAC prepares the next sample, achieving fast frequency switching without compromising settling time for each individual conversion.
2Speed
If multiple parallel DACs are used with switching to achieve fast frequency switching, then frequency switching speed is improved, but switching noise is generated
Solution Approach 1:
The patent applies preliminary dithering to the digital samples before they are converted by the DACs. This preliminary action adds a small random signal to the digital input, which randomizes the quantization error and reduces the visibility of spurs and switching noise in the output spectrum, making the switching between multiple DACs less noisy.
Solution Approach 2:
The patent converts the potentially harmful switching noise and quantization errors into a beneficial form by applying dithering. The randomization transforms deterministic switching artifacts into a more uniform noise floor that is easier to filter and less problematic for signal quality, effectively turning the switching harm into an acceptable characteristic.
3Measurement precision
If DAC sampling rate is increased to reduce quantization noise, then quantization noise is reduced, but hardware complexity and cost increase
Solution Approach 1:
Instead of using a single high-speed DAC with high sampling rate, the patent segments the conversion function across multiple lower-speed DACs operating in parallel. Each DAC operates at a reduced sampling rate processing alternating samples, which reduces the hardware complexity and cost of each individual DAC while maintaining the overall effective sampling rate through the switching mechanism.
Data Source
AI summary
A direct digital synthesis (DDS) device includes a first digital to analog converter (DAC) and a second DAC, wherein the first and second DACs are configured to respectively process first and second samples of a digital amplitude signal. The DDS device also includes a switch configured to receive first and second DAC output signals from the first and second DACs, respectively, and selectively switch among at least the first DAC output signal and the second DAC output signal to generate a combined signal. The DDS device also includes a signal mixer configured to receive the combined signal and a mixer clock signal, wherein the signal mixer is a multi-mode mixer further configured to operate in (i) a pass-through mode where the combined signal is provided as a mixed signal, and (ii) a mixing mode where the combined signal is mixed with the mixer clock signal, to generate the mixed signal.