Multi-Data Line Architecture for Fluid Ejection Memory Access
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Solution Overview
Problem
In fluid ejection devices, such as printheads, the limited number of address lines restricts the address space and bandwidth for memory access, leading to constrained data storage and slow operation.
Innovation Solution
Implementing a multi-data line arrangement where multiple data lines are shared among fluid ejection devices to increase address space and bandwidth, and using interleaved memory access with multiple decoders and pass gates to control signal durations, allowing for simultaneous access to multiple memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a limited number of address lines are used in fluid ejection devices, then the device complexity is reduced, but the address space and bandwidth for memory access are restricted
Solution Approach 1:
The patent transitions from a single-data line architecture to a multi-data line architecture, adding a new dimension to the memory access pathway. This allows multiple data lines to be shared among multiple fluid ejection devices, effectively expanding the address space without proportionally increasing the number of address lines. The multi-dimensional data path enables parallel data transmission across multiple devices.
Solution Approach 2:
The data lines are designed to serve multiple functions: they act as address lines for individual devices while simultaneously serving as data lines when shared across multiple devices. This multi-functionality allows the same physical infrastructure to support both addressing and data transmission, maximizing the utilization of available lines and expanding effective address space.
2Device complexity
If a limited number of address lines are used in fluid ejection devices, then the device complexity is reduced, but the bandwidth for memory access is reduced
Solution Approach 1:
By introducing multiple data lines as a new dimension to the memory access architecture, the system achieves higher bandwidth without proportionally increasing address line count. The parallel data paths enabled by multiple shared data lines allow simultaneous data transmission to and from multiple fluid ejection devices, significantly boosting overall data access bandwidth.
Solution Approach 2:
The interleaved memory access mechanism enables continuous data transmission by alternating between multiple data lines and devices. While one data line is transmitting data, another can be preparing or receiving data, ensuring that the data access bandwidth is maximized through continuous productive action across the multi-line infrastructure.
3Quantity of substance
If interleaved memory access with multiple decoders is implemented, then the address space and bandwidth are increased, but the device complexity is increased
Solution Approach 1:
The memory access system is segmented into multiple decoders, each responsible for specific address ranges or devices. This segmentation allows the total address space to be divided and managed by multiple smaller decoder units, achieving expanded address space capability while distributing the complexity across modular components rather than requiring a single complex decoder.
Solution Approach 2:
Multiple decoders are merged into a coordinated system where they work together through interleaved access patterns. The combined functionality of multiple decoders provides expanded addressing capability, while their coordinated operation through shared data lines and interleaved timing reduces the overall system complexity compared to a single monolithic decoder handling all addressing.
Data Source
AI summary
In some examples, a system includes a plurality of fluid ejection devices, a fluid ejection controller, and a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices. A first data line of the plurality of data lines communicates data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and a second data line of the plurality of data lines communicates data of a second memory of the first fluid ejection device.