Multi-DCO PLL Scaling for Spur Suppression and Low Jitter
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Solution Overview
Problem
Fractional-N frequency synthesizers generate unwanted low-frequency spurs due to dual-modulus dividers, making them impractical for many applications unless spur reduction techniques are employed, which can limit their performance and require additional circuitry to reduce jitter.
Innovation Solution
A phase-locked loop (PLL) integrated circuit with multiple digitally-controlled oscillators (DCOs) slaved to a common feedback loop filter, using scaling circuits to normalize control signals and generate multiple periodic PLL output signals with equivalent fractional frequency offsets, and incorporating a digital noise cancellation mechanism to enhance spur suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fractional-N frequency synthesizers are used to achieve fine frequency resolution, then frequency resolution is improved, but unwanted low-frequency spurs are generated
Solution Approach 1:
The patent converts the harmful spurs generated by dual-modulus dividers into a beneficial signal by using them as a reference for digital noise cancellation. The spurs are detected by the digital phase detector and used to generate cancellation signals that subtract the spur components from the output, transforming the harmful interference into a useful reference for suppression.
Solution Approach 2:
The patent introduces digital noise cancellation circuitry as an intermediary between the fractional-N divider and the output. This intermediary detects the spur signals, processes them through digital filtering and scaling, and generates cancellation signals that are combined with the main output to eliminate the harmful spurs while preserving the fine frequency resolution.
2Adaptability or versatility
If multiple fractional-N dividers are provided to generate different frequency outputs, then frequency versatility is improved, but jitter increases
Solution Approach 1:
The patent merges multiple fractional-N dividers into a single shared architecture where multiple dividers operate in parallel but share common digital noise cancellation resources. The digital phase detector and filtering circuitry are shared among all dividers, allowing multiple frequency outputs to be generated simultaneously while maintaining low jitter through coordinated noise cancellation across all channels.
Solution Approach 2:
The patent creates a universal digital noise cancellation system that serves multiple fractional-N dividers simultaneously. The same digital filtering, scaling, and cancellation circuitry is used for all frequency outputs, providing consistent jitter reduction across all channels while maintaining the ability to generate different frequencies with equivalent performance.
3Object-generated harmful factors
If digital noise cancellation is implemented to suppress spurs, then spur suppression is improved, but device complexity increases
Solution Approach 1:
The patent replaces traditional analog noise cancellation mechanisms with digital signal processing techniques. Instead of using complex analog filtering and cancellation circuits, the invention uses digital phase detection, digital filtering, and digital signal combination to achieve spur suppression. This substitution of digital for analog approaches reduces component count and simplifies the overall circuit architecture while maintaining effective spur cancellation.
Data Source
AI summary
A phase-locked loop (PLL) integrated circuit includes multiple digitally-controlled oscillators (DCOs), which are slaved to the same feedback loop filter. This PLL includes a frequency control circuit, which is configured to generate a control signal and is responsive to a first periodic reference signal (e.g., REFCLK). The plurality of DCOs include a corresponding plurality of independently-programmable fractional dividers, which are configured to generate a respective plurality of periodic PLL output signals of different frequency in response to a second periodic reference signal (e.g., SYSCLK). The plurality of DCOs include corresponding scaling circuits, which are each responsive to the control signal. The plurality of scaling circuits are configured to scale the control signal to different degrees to thereby make effective gains of the DCOs more nearly equal.