Multi-Deck HBM Bonding Structure for Lower-Etch Fabrication
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently stacking multiple decks with high bandwidth memory (HBM) structures while minimizing fabrication costs and increasing production yield and capacity density.
Innovation Solution
A semiconductor device is designed with multiple decks of semiconductor structures stacked along a vertical direction, using dielectric layers for bonding and contact structures that extend through or around these decks, allowing for reduced etching processes and direct bonding techniques, thereby reducing fabrication costs and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple decks of semiconductor structures are stacked to increase memory density, then capacity density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The semiconductor device is divided into multiple decks (first deck, second deck, third deck) that are stacked vertically. Each deck contains semiconductor structures that can be independently formed and bonded, allowing complex memory capacity to be achieved through modular stacking rather than creating a single complex structure. This segmentation enables parallel fabrication processes and reduces overall fabrication complexity.
Solution Approach 2:
The patent transitions from planar memory arrangement to three-dimensional stacking along a first direction. Multiple decks are positioned at different vertical levels, with dielectric layers bonding structures from different decks together. This dimensional transition allows significant increase in memory capacity density without proportionally increasing fabrication complexity, as the stacking approach reuses similar fabrication processes across multiple levels.
2Manufacturing precision
If conventional etching processes are used for each deck, then manufacturing precision is maintained, but production time and cost increase
Solution Approach 1:
The patent merges the etching processes for multiple decks into a single simultaneous etching operation. Contact structures are formed extending through multiple decks at the same time, rather than etching each deck separately in sequence. This consolidation maintains manufacturing precision through consistent etching parameters applied uniformly across all decks while dramatically improving production efficiency by eliminating repeated process cycles.
Solution Approach 2:
The patent performs preliminary alignment and positioning of contact structures before the actual etching process. Contact holes are formed extending through multiple decks with pre-planned pathways, allowing subsequent etching to proceed efficiently without requiring multiple alignment steps. This preliminary action ensures manufacturing precision is maintained while reducing total production time.
3Reliability
If more etching cycles are performed to create contact structures through multiple decks, then connectivity is improved, but fabrication cost and time increase
Solution Approach 1:
The patent combines multiple contact structure formation operations into a single integrated process. Contact structures extend continuously through multiple decks (first deck, second deck, third deck) and are formed in one etching and filling cycle rather than separate operations for each deck. This merging ensures reliable connectivity across all decks while eliminating the time loss associated with multiple sequential etching cycles.
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing a high bandwidth memory (HBM) with multiple decks. An example semiconductor device includes multiple decks of semiconductor structures stacked along a first direction, multiple dielectric layers between the multiple decks of semiconductor structures, and multiple groups of contact structures extending along the first direction. The multiple decks of semiconductor structures include at least a first deck of semiconductor structures and a second deck of semiconductor structures. The multiple dielectric layers extend along a second direction perpendicular to the first direction and include at least a first dielectric layer between the first deck of semiconductor structures and the second deck of semiconductor structures. The first deck of semiconductor structures is bonded to the second deck of semiconductor structures by the first dielectric layer.