Multi-Deck Memory Architecture for High Density and Low Power
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Solution Overview
Problem
Current memory devices face limitations in memory cell density, read/write speeds, reliability, data retention, and power consumption, particularly in volatile memory types like DRAM, which require frequent refreshing and result in significant power consumption.
Innovation Solution
A multi-deck memory device architecture incorporating self-selecting memory (SSM) cells and phase change memory cells with separate storage elements and selectors, allowing for improved read/write speeds, increased density, and reduced power consumption by leveraging ion migration properties and distinct programming states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory devices like DRAM are used to achieve fast read/write speeds, then read/write speed is improved, but power consumption increases due to frequent refreshing
Solution Approach 1:
The memory device is segmented into multiple decks, with each deck containing a specific type of memory cell (SSM or PCM). This segmentation allows the system to leverage the speed advantages of SSM cells while using PCM cells for non-volatile storage, thereby reducing the need for frequent refreshing and lowering overall power consumption while maintaining fast read/write speeds for frequently accessed data.
Solution Approach 2:
The patent changes the physical and chemical parameters of the memory cells by using different materials and structures (SSM cells with ion migration properties and PCM cells with phase change properties). This allows the system to achieve both fast read/write speeds and non-volatile storage characteristics, eliminating the need for frequent refreshing and reducing power consumption.
2Quantity of substance
If memory cell density is increased to improve storage capacity, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangements to three-dimensional multi-deck structures. By stacking multiple decks vertically, the system achieves higher memory cell density without significantly increasing the lateral footprint, thereby avoiding the need for extremely precise manufacturing processes that would be required for further lateral scaling.
Solution Approach 2:
The memory device employs a nested structure where multiple decks are stacked vertically, with each deck containing memory cells that are interconnected through shared bit lines and word lines. This nesting approach allows for high-density storage by efficiently utilizing vertical space while maintaining manageable manufacturing complexity through modular design.
3Reliability
If separate memory storage elements and selectors are used in phase change memory cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The selector devices in the patent serve multiple functions: they act as switches for selecting specific memory cells, provide non-volatile storage capabilities through their own resistive states, and enable cross-point memory architecture for high-density storage. This multi-functionality reduces the need for separate dedicated components, thereby managing device complexity while improving reliability and data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances memory cell density, read/write speeds, and reduces power consumption by utilizing SSM and phase change memory cells, maintaining data integrity without the need for frequent refreshing, thus improving overall memory performance and efficiency.
Implementation Method 1
leveraging ion migration properties
Implementation Method 2
phase change memory cells
Data Source
AI summary
Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.