Multi-deck Memory Device with Independent Data Lines
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Solution Overview
Problem
Conventional memory devices have inefficient line structures that affect throughput, making them unsuitable for certain applications due to shared access and data lines, which can lead to reduced performance in memory operations.
Innovation Solution
The memory device employs separate access and data lines for each deck of memory cell strings, along with dedicated driver and buffer circuits, allowing for independent operation of multiple decks during memory operations, enhancing throughput and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory devices use shared access lines and data lines for multiple decks, then device complexity is reduced, but throughput is limited due to inability to access multiple decks concurrently
Solution Approach 1:
The patent divides the memory device into multiple independent decks, where each deck has its own separate access lines and data lines. This segmentation allows concurrent access to multiple decks simultaneously, thereby increasing throughput without requiring complex shared line arbitration mechanisms.
Solution Approach 2:
The patent introduces a new dimension of parallelism by stacking multiple decks vertically, where each deck operates independently with dedicated access lines. This dimensional approach enables simultaneous operations across decks, effectively increasing throughput without proportionally increasing access line complexity.
2Productivity
If conventional memory devices use shared data lines for multiple decks, then capacitance is reduced, but read/write operations cannot be performed concurrently on multiple decks
Solution Approach 1:
The patent assigns dedicated data lines to each deck, enabling independent and concurrent read/write operations on multiple decks. This segmentation of data lines eliminates the need for complex multiplexing and arbitration logic that would be required for shared data lines.
Solution Approach 2:
Each deck functions as an independent memory unit with its own data lines, allowing the memory device to perform multiple operations simultaneously on different decks. This multi-functionality approach increases productivity without requiring additional complex control mechanisms.
3Productivity
If conventional memory devices use shared access lines between decks, then manufacturing is simplified, but erase operations cannot be performed on multiple decks simultaneously
Solution Approach 1:
The patent provides separate access lines for each deck, enabling simultaneous erase operations on multiple decks. This segmentation allows parallel processing of erase commands across different decks, significantly improving erase operation throughput without requiring complex line sharing arbitration.
Solution Approach 2:
The patent structures the access lines such that each deck is independently accessible from the outset, allowing erase operations to be initiated and executed concurrently on multiple decks without requiring sequential arbitration or time-multiplexing of shared lines.
Data Source
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AI summary
Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.