Multi-Deck Non-Volatile Memory Layout With Smaller Termination Tiles
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Solution Overview
Problem
Current multi-deck non-volatile memory architectures have a significant termination tile area that increases the overall partition size, leading to inefficient use of die space and potential yield reduction due to the 1:2 ratio of termination tile width to main tile width, resulting in faster charging times for edge memory cells and inconsistent loading.
Innovation Solution
The proposed solution reduces the termination tile area by altering the bitline and wordline routing to a 1:4 ratio, cutting conductor length in half and maintaining consistent loading, which reduces the termination tile area by half and eliminates the need for additional deselect bias circuits, thereby optimizing die size and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If termination tile width is maintained at 1:2 ratio to main tile width, then edge memory cells receive faster charging times, but termination tile area increases overall partition size and reduces die space efficiency
Solution Approach 1:
The patent changes the termination tile width ratio from the conventional 1:2 to a new ratio between 1:3 and 1:5. This parameter change reduces the termination tile area while maintaining consistent loading conditions through adjusted conductor dimensions, thereby reducing overall partition size without sacrificing charging performance
Solution Approach 2:
The patent introduces asymmetric compensation by making conductors in termination tiles longer or wider than those in main tiles. This asymmetric design compensates for the reduced termination tile area, ensuring that edge memory cells still receive adequate charging current despite the smaller tile dimensions
2Area of stationary object
If termination tile area is reduced, then die size decreases, but loading consistency across tiles may be compromised
Solution Approach 1:
The patent simultaneously adjusts multiple parameters: termination tile width ratio (to 1:3 or 1:5), conductor length, and conductor width. These coordinated parameter changes allow area reduction while maintaining consistent electrical loading by compensating with larger conductor cross-sections in termination tiles
Solution Approach 2:
The patent applies local quality by making conductors in termination tiles specifically longer or wider than those in main tiles. This localized adjustment ensures that the reduced termination tile area does not compromise loading consistency, as the enhanced conductor dimensions locally compensate for the smaller tile size
3Stability of the object's composition
If conventional termination tile routing is used, then all tiles have consistent loading, but additional deselect bias circuits are required increasing device complexity
Solution Approach 1:
The patent extracts and eliminates the need for additional deselect bias circuits in termination tiles by reconfiguring the bitline and wordline routing. The new routing approach with adjusted termination tile dimensions and conductor proportions inherently provides consistent loading, removing the requirement for these additional circuits and thereby reducing device complexity
Data Source
AI summary
In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.