Multi-Decoder Check-Node Ordering for LDPC Codeword Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current communication systems face challenges in efficiently decoding encoded input signals using multiple decoding mechanisms, which leads to increased hardware costs and performance gaps, especially for short length LDPC codes and serial decoders.
Innovation Solution
A receiver architecture that employs a plurality of decoders configured to process check nodes in different orders, allowing for simultaneous or sequential decoding to determine valid codewords, thereby reducing the need for custom hardware for each encoding mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple decoding mechanisms are used to improve error-correcting performance, then reliability is improved, but device complexity and hardware costs increase
Solution Approach 1:
The patent implements a universal decoder architecture that can handle multiple encoding mechanisms (LDPC, polar, and other linear block codes) using a single device. The decoder is configured to process check nodes in different orders based on the encoding type, allowing one decoder to perform multiple functions that previously required separate decoders for each code type, thereby reducing hardware complexity while maintaining reliability
Solution Approach 2:
The patent changes the processing order parameter of check nodes based on the encoding mechanism being used. By dynamically adjusting the check node processing order (e.g., different orders for LDPC vs. polar codes), the same decoder hardware can adapt to different encoding schemes, achieving multi-functionality without increasing device complexity
2Manufacturing precision
If custom hardware is designed for each encoding mechanism, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent creates a universal decoder that can manufacture and deploy a single hardware design for multiple encoding mechanisms. Instead of producing separate custom hardware for each code type, the universal decoder can be manufactured once and configured to handle LDPC, polar, and other codes through software or configuration changes, significantly improving ease of manufacture while maintaining decoding accuracy through specialized processing orders
3Device complexity
If sequential decoding is used to reduce hardware complexity, then device complexity is reduced, but productivity deteriorates due to increased decoding latency
Solution Approach 1:
The patent implements a dynamic decoder architecture that can switch between sequential processing (for lower complexity) and parallel processing (for lower latency) based on the specific encoding mechanism and performance requirements. The system dynamically adjusts the check node processing strategy, allowing it to optimize between complexity and latency trade-offs rather than being fixed in one mode
Data Source
AI summary
There is provided a method, computer program and receiver comprising a plurality of decoders for causing the receiver to perform: receiving (901) an encoded input signal, y, at each of the plurality of decoders; decoding (902), at each of the plurality of decoders, the input signal by processing check nodes in a respective order to obtain a plurality of decoded signals, x1, . . . , xL, the respective orders being different for the plurality of decoders; determining (903) a plurality of valid codewords from the plurality of decoded signals; and determining (904) an output codeword as an estimate of the input signal from the plurality of valid codewords.