Multi-degree Branch Predictor Resolving Speed-Accuracy Tradeoff
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Solution Overview
Problem
Modern processors face challenges in achieving accurate branch predictions while maintaining high processing throughput, due to limitations in the size of history tables used in branch predictors, which affect both speed and accuracy.
Innovation Solution
A multi-degree branch predictor is implemented, where multiple prediction subcircuits with different-sized history tables operate in degrees, generating predictions in different clock cycles. Smaller history tables provide fast initial predictions, while larger tables refine these predictions, with later degrees overriding earlier ones when discrepancies occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If larger history tables are used in branch predictors, then prediction accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The branch predictor is divided into multiple prediction subcircuits, each with different-sized history tables (different degrees). This segmentation allows the system to use smaller tables for fast predictions and larger tables for more accurate predictions, resolving the contradiction between speed and accuracy by distributing the prediction function across multiple specialized subcircuits.
Solution Approach 2:
The patent introduces a temporal dimension to the prediction process by having prediction subcircuits operate in different clock cycles. Smaller history tables operate in earlier clock cycles providing fast initial predictions, while larger tables operate in later cycles providing refined predictions. This transforms the speed-accuracy tradeoff from a spatial constraint into a temporal sequence.
2Speed
If smaller history tables are used in branch predictors, then processing speed is improved, but prediction accuracy deteriorates
Solution Approach 1:
Smaller history tables in earlier prediction subcircuits perform preliminary predictions in initial clock cycles. These preliminary actions provide fast predictions that can be used immediately, while larger history tables in later subcircuits perform refined predictions that can correct or override the preliminary ones, ensuring both speed and accuracy are achieved.
Solution Approach 2:
The system implements feedback through the multi-degree architecture where predictions from smaller history tables are subject to verification and potential override by larger history tables. This feedback mechanism allows the system to maintain high speed through initial quick predictions while ensuring accuracy through subsequent verification by more comprehensive history tables.
3Measurement precision
If multiple prediction subcircuits with different history table sizes are used, then both speed and accuracy are balanced, but device complexity increases
Solution Approach 1:
Multiple prediction subcircuits implement a common branch prediction scheme, providing universality in the prediction methodology while varying only the history table sizes. This multi-functionality approach allows different subcircuits to serve different purposes (speed vs. accuracy) while maintaining a unified prediction framework, reducing the complexity increase compared to having completely different prediction mechanisms.
Data Source
AI summary
A multi-degree branch predictor is disclosed. A processing circuit includes an instruction fetch circuit configured to fetch branch instructions, and a branch prediction circuit having a plurality of prediction subcircuits. The prediction subcircuits are configured to store different amounts of branch history data with respect to other ones, and to receive an indication of a given branch instruction in a particular clock cycle. The prediction subcircuits implement a common branch prediction scheme to output, in different clock cycles, corresponding predictions for the given branch instruction using the different amounts of branch history data and cause, instruction fetches to be performed by the instruction fetch circuit. The prediction subcircuits are also configured to override, in subsequent clock cycles, instruction fetches caused by prediction subcircuits with comparatively less branch history data based on contrary predictions performed in subsequent clock cycles by prediction subcircuits with more branch history data.