Multi-Depth Trench Alignment Mark for Semiconductor Wafer
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Solution Overview
Problem
The resolution of alignment marks in semiconductor devices is limited by the size of the trench width, leading to reduced accuracy and optical resolution during wafer alignment processes.
Innovation Solution
A method involving a substrate with a hard mask layer and multiple mask patterns is used, where the second mask pattern has a top surface lower than the first mask pattern, and specific gaps between patterns allow for deeper trench formation in the cutting line region, enhancing image contrast and optical resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the trench width of the alignment mark is reduced to accommodate smaller device features, then the device size is reduced, but the optical resolution of the alignment mark deteriorates
Solution Approach 1:
The invention transitions from a single-depth trench structure to a multi-depth trench structure. By forming first trenches and second trenches with different depths in the substrate, the alignment mark gains an additional dimensional characteristic (depth variation) that enhances its optical detectability without requiring increased trench width, thus resolving the contradiction between device miniaturization and alignment mark resolution.
Solution Approach 2:
The invention applies different trench depths to different regions of the alignment mark structure. First trenches are formed at one depth while second trenches are formed at a greater depth, creating local variations in the alignment mark's physical properties. This local differentiation enhances the optical contrast and resolution of the alignment mark without affecting the overall device feature size.
2Measurement precision
If the alignment mark structure is made more complex to improve resolution, then the optical resolution improves, but the manufacturing process complexity increases
Solution Approach 1:
The invention performs preliminary patterning actions by forming a patterned mask layer with first and second regions before etching the substrate. This pre-established mask pattern guides the subsequent formation of multi-depth trenches, allowing the complex alignment mark structure to be created through a systematic, step-by-step process rather than a single complex operation, thereby managing manufacturing complexity while achieving high resolution.
Solution Approach 2:
The invention segments the alignment mark formation process into distinct stages: forming first trenches at a first depth, then forming second trenches at a second depth. This segmentation of the manufacturing process allows each etching step to be controlled independently, managing process complexity while achieving the desired multi-depth structure that enhances optical resolution.
Data Source
AI summary
The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.