Multi-Detector Error Cancellation for Low-Latency Noise Feedback

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Solution Overview

Problem

Conventional low latency loops used for tracking low frequency changes in data signals often introduce excessive errors leading to large loop noise, and they typically lack the necessary loop update gain due to high latency issues.

Innovation Solution

A data processing circuit with first and second data detectors and an error cancellation circuit, where the second data detector provides low latency error feedback, and the error cancellation circuit combines error signals to generate a feedback signal that modifies the input, reducing latency while maintaining loop gain by using a combination of decision feedback equalizers and Viterbi detectors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional low latency loop is used to track low frequency changes in the data signal, then the loop can respond quickly to changes, but it introduces excessive errors leading to large loop noise

Engineering Contradiction:
Improveloop response speedVSAvoiderror rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the detection function into two separate detectors: a low latency detector for quick response and a high accuracy detector for reliable error detection. Each detector processes the signal independently with different latency characteristics, allowing the system to combine the advantages of both speed and accuracy without the errors inherent in a single low latency design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error cancellation circuit serves as an intermediary that combines the error signals from both detectors. It subtracts the low latency detector's error signal from the high accuracy detector's error signal, effectively canceling out the latency-induced errors while maintaining the quick response capability of the low latency detector.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If a low latency detector is used to track low frequency changes, then rapid error corrections can be made, but the loop gain becomes insufficient due to latency

Engineering Contradiction:
Improveerror correction speedVSAvoidloop update gain
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent merges the error signals from both the low latency detector and the high accuracy detector through the error cancellation circuit. This combination allows the system to maintain the high loop update gain necessary for tracking low frequency changes while preserving the rapid error correction capability of the low latency detector, effectively resolving the trade-off between speed and gain.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple detectors are used to cancel errors, then noise can be reduced and loop gain maintained, but the device complexity increases

Engineering Contradiction:
Improvenoise levelVSAvoiddetector circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error cancellation circuit performs multiple functions: it combines error signals from both detectors, cancels latency-induced errors, maintains loop gain, and reduces noise. This multi-functional approach achieves reliable noise reduction and gain maintenance without requiring separate complex circuits for each function, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8862972B2Low latency multi-detector noise cancellation
Publication Date: 2014.10.14 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8862972B2 patent drawing
  • US8862972B2 patent drawing
  • US8862972B2 patent drawing

AI summary

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.