Multi-Device Cached Commands for Concurrent CXL.io Management
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Solution Overview
Problem
The existing Compute Express Link (CXL.io) protocol for managing peripheral devices in high-performance computing environments requires one-to-one communication, leading to time-consuming management and limited concurrency due to kernel space memory constraints, especially when dealing with numerous and changing devices.
Innovation Solution
Implementing a modified CXL.io protocol with a cached buffers flag that allows devices to access host memory using coherent caches, enabling concurrent command execution and data exchange without DMA transfers, and supporting multicast and broadcast commands for multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one-to-one communication protocol is used for device management, then device control reliability is improved, but management time increases and productivity decreases
Solution Approach 1:
The patent merges multiple device management operations into a single multicast command that can be received by multiple devices simultaneously. The host sends one command that is replicated and delivered to N devices, allowing batch configuration and management operations that would otherwise require N separate one-to-one communications, thus improving productivity while maintaining reliable device control
Solution Approach 2:
The command protocol is enhanced to support both traditional one-to-one communication and new multicast/broadcast modes. The universal command structure can be used for single device control or simultaneously addressed to multiple devices, providing multi-functionality that resolves the contradiction between reliable individual control and efficient batch management
2Reliability
If DMA transfers are used for data exchange, then data transfer reliability is improved, but kernel space memory usage increases and device concurrency is limited
Solution Approach 1:
The patent introduces user space as an intermediary layer between the host and devices for data exchange. Instead of requiring all data transfers to go through kernel space DMA buffers, the system uses user space memory regions that can be directly accessed by devices through the cache-coherent fabric, bypassing the kernel space memory limitation while maintaining transfer reliability through the established fabric protocols
Solution Approach 2:
The patent changes the memory access dimension by moving from kernel space (OS-managed) to user space (application-managed) memory regions. This dimensional shift in memory management allows vastly larger memory regions to be allocated for device data exchange, overcoming the few-megabyte kernel space limitation and enabling concurrent operations with numerous devices
3Reliability
If kernel space memory is used for DMA transfers, then data transfer security is improved, but memory capacity decreases and adaptability worsens
Solution Approach 1:
The patent segments the memory management responsibilities between kernel space and user space. Kernel space retains security-critical functions while user space handles large-scale data exchange operations. This segmentation allows the system to maintain security through kernel-space authentication and authorization while achieving high device concurrency through user-space memory resources that are not constrained by kernel space limitations
Data Source
AI summary
An example method of processing a command at a device sent by a host in a computing system, the host comprising a central processing unit (CPU) and host memory, is described. The method includes: receiving, at the device, the command from the host; parsing, by the device, the command to identify a flag in the command that is set and to obtain a first address that references a source buffer in the host memory; and reading, by the device in response to the flag being set, source data from the source buffer by reading from a coherent cache on the device using the first address, a cache coherency manager in the host managing the coherent cache.