Multi-Die ASIC Partitioning for Scalable Functions and Lower I/O Power
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Solution Overview
Problem
ASIC implementations with multiple identical die in a multi-chip-module face increased power consumption due to die-to-die I/O interfaces, while a single monolithic die consumes more power when the total quantity of instantiated functions is reduced.
Innovation Solution
A semiconductor wafer design with processing cores spaced apart by a target distance, allowing for standard routing and communication between cores via I/O interfaces, including routing and rerouting based on address tables and fault detection, with ESD protection, to mitigate power consumption and enable scalable function scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiple identical die are connected in a multi-chip-module, then power consumption is reduced for high-functionality ASICs, but power consumption increases due to die-to-die I/O interfaces
Solution Approach 1:
The patent segments the ASIC functionality into multiple identical die, each containing a subset of processing functions. This segmentation allows the system to scale functionality by adding die while managing power consumption through selective activation. Each die can be independently controlled, enabling the system to power down unused die and their associated I/O interfaces, thus resolving the contradiction between functionality scaling and power consumption.
2Use of energy by moving object
If a single monolithic die is used, then power consumption is reduced for low-functionality ASICs, but power consumption increases when total quantity of instantiated functions is reduced
Solution Approach 1:
The patent implements dynamic configurability where the ASIC can adapt its functionality by selectively activating or deactivating specific die based on the required function quantity. This dynamic approach allows the system to optimize power consumption by powering down unused die while maintaining adaptability to different functionality requirements. The system transitions from a static monolithic design to a dynamic multi-die configuration that can be reconfigured based on operational needs.
3Productivity
If multiple identical die are connected in a multi-chip-module, then functionality can be scaled by adding die, but power consumption increases due to additional die-to-die I/O interfaces
Solution Approach 1:
The patent applies partial action by activating only the necessary subset of die required for the current functionality level, rather than powering all die. This allows functionality to be scaled by having additional die available (excessive capacity) while only consuming power for the active portion. The system can scale functionality from 1 to N die without proportionally increasing power consumption, as unused die remain in a low-power state.
Data Source
AI summary
A semiconductor wafer is provided including: processing cores; and die structures each including at least one processing core. Each processing core includes a set of first input output (I/O) interfaces configured for communication between the processing core and a second processing core, wherein the processing core and the second processing core are included in a first die structure of the die structures. Each processing core includes a second input output (I/O) interface configured for communication between the processing core and a third processing core, wherein the third processing core is included in a second die structure of the die structures. The processing cores are spaced apart by a target distance associated with separating one or more processing cores or one or more die structures from the semiconductor wafer.