Wafer-Level Multi-Die Bridge Interconnects for Dense Chiplet Routing
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Solution Overview
Problem
Current die-to-die interconnect schemes in IC packaging face challenges with large die area consumption and long wire lengths, limiting signal bandwidth and bump pitch, which negatively affect device performance in System on a Chip (SoC) architectures.
Innovation Solution
The implementation of high-density interconnect bridge structures formed directly on chiplets using silicon metal layer processes, such as deposition and lithographic processes, which enable very high density interconnect pitch and reduced pad pitch by minimizing die-to-die circuit area and reducing conductive trace lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If embedded multi-die interconnect bridge structures are used, then high wiring density is achieved, but large die area consumption occurs
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical interconnect structures by forming bridge structures that extend upward from the substrate, allowing wires to route in the vertical dimension rather than only laterally across the die surface
Solution Approach 2:
The bridge structures are embedded within and integrated into the package substrate, with the substrate providing mechanical support while the bridge structures provide electrical interconnect, creating a nested configuration where one structure is embedded in another
2Strength
If standard silicon wafer manufacturing processing is used, then robust mechanical protection is achieved, but long wire lengths are required
Solution Approach 1:
The invention introduces vertical 3D routing through bridge structures that connect dies stacked in the vertical direction, dramatically reducing the lateral wire length compared to traditional planar routing while maintaining mechanical protection through the substrate embedding
3Quantity of substance
If bridge structures are formed directly on chiplets, then high-density interconnect pitch is achieved, but additional manufacturing steps are required
Solution Approach 1:
The patent combines the bridge structure formation process with the existing silicon wafer fabrication process, using standard deposition and lithographic techniques to form conductive traces on the bridge structures, thereby integrating the high-density interconnect feature into the conventional manufacturing flow
Solution Approach 2:
The bridge structures serve multiple functions: providing mechanical support between dies, enabling electrical interconnect, and facilitating high-density routing, all while being formed using standard silicon processing equipment and techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher signal bandwidth and lower power consumption in SoC architectures by allowing for high-density lateral connections between neighboring dies, resulting in cost-effective, high-performance SoC structures with reduced active area usage and shorter interconnect lengths.
Implementation Method 1
forming a plurality of conductive traces on the inorganic dielectric layer
Implementation Method 2
lithographic processes, which enable very high density interconnect pitch
Data Source
AI summary
Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.