Multi-Die Cache Coherency Using Proxy and Global Cache Controllers
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Solution Overview
Problem
In multi-die processor-based systems, maintaining cache coherency across separate dies introduces significant performance issues due to additional latency and bandwidth limitations of inter-die and inter-socket communications.
Innovation Solution
A multiple-level hierarchy cache coherency architecture is implemented, utilizing proxy cache controller circuits on each die and a global cache controller circuit to maintain cache coherency while allowing local cache memories to service memory access requests within their die, reducing latency by minimizing off-die communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single global cache controller manages all cache coherency requests in a multi-die system, then cache coherency is maintained, but memory access latency increases significantly due to inter-die communication requirements
Solution Approach 1:
The patent divides the cache coherency management function into multiple segments by introducing proxy cache controllers on each die. Each proxy cache controller independently manages coherency for its local die, reducing the need for cross-die communication while maintaining overall system coherency through the global cache controller's coordination.
Solution Approach 2:
The proxy cache controllers act as intermediary elements between local CPU cores and the global cache controller. These intermediaries handle routine coherency operations locally, filtering out the need for frequent inter-die communications and reducing latency for most memory access requests.
2Reliability
If all memory access requests are routed through the global cache controller, then cache coherency is maintained, but system bandwidth is reduced due to inter-die communication limitations
Solution Approach 1:
The patent segments the cache coherency management workload across multiple proxy controllers distributed on different dies. This segmentation allows parallel processing of coherency operations locally on each die, reducing the bandwidth burden on inter-die communication channels while maintaining comprehensive cache coherency.
Solution Approach 2:
Each proxy cache controller provides localized coherency management optimized for its specific die, enabling high-speed local operations without requiring bandwidth-intensive communication with the global controller for routine operations.
3Loss of time
If proxy cache controllers service memory requests independently within their die, then memory access latency is reduced, but cache coherency maintenance becomes more complex
Solution Approach 1:
The proxy cache controllers are designed to autonomously service memory requests within their local die without constant intervention from the global cache controller. This self-service capability reduces latency by eliminating unnecessary communication overhead while maintaining coherency through localized control.
Solution Approach 2:
The system implements feedback mechanisms where proxy cache controllers communicate coherency state information to the global cache controller, allowing the global controller to make informed decisions about when inter-die coordination is necessary, thus balancing independence with coherency requirements.
Data Source
AI summary
Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions