Configurable Multi-Die Clock Networks for Low-Skew Routing
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Solution Overview
Problem
Conventional clock circuitries in integrated circuits (ICs) are inflexible, leading to issues such as clock skew and timing uncertainty, which become more problematic as ICs increase in size.
Innovation Solution
A configurable clock architecture is introduced, utilizing horizontal and vertical routing tracks with switch box circuitries to form regional and global clock circuitries, allowing for customizable clock trees based on design constraints, reducing clock skew and insertion delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional regional clocks are driven only from edges and global clocks only from center, then clock circuitry architecture is simple, but flexibility is poor and clock skew increases as IC size grows
Solution Approach 1:
The clock distribution network is segmented into multiple regional clock circuits distributed across different locations (edges and center) rather than a single centralized clock source. Each regional clock circuit can be independently configured to serve specific resource regions, enabling flexible clock distribution adapted to IC size and layout while maintaining manageable complexity through modular organization.
Solution Approach 2:
The clock circuitry is designed with universal routing tracks (horizontal and vertical) that can be configured to form different clock distribution patterns. The same routing infrastructure serves multiple functions: regional clock distribution from edges, global clock distribution from center, and hybrid configurations, eliminating the need for separate dedicated pathways for each clock type.
2Area of stationary object
If IC size increases, then more resources are available, but clock skew and timing uncertainty increase
Solution Approach 1:
Large ICs are divided into multiple regions, each served by regional clock circuits located strategically within those regions. This segmentation ensures that clock signals travel shorter distances to reach resources in each region, reducing cumulative skew and timing uncertainty across the entire IC while still providing comprehensive resource coverage.
Solution Approach 2:
Different regions of the IC receive clock signals from locally positioned regional clock circuits rather than a single distant source. This local quality approach optimizes timing precision for each specific region by minimizing signal path length and allowing regional clock configuration to match the specific timing requirements of local resource density and critical paths.
3Reliability
If fixed clock distribution paths are used, then routing is simple, but ability to reduce clock skew is limited
Solution Approach 1:
The clock distribution routing is made dynamic and reconfigurable through programmable logic that can alter the activation state of routing tracks and switch box circuitries. This allows the clock network to adapt its path and configuration based on design requirements, enabling optimal clock skew reduction for different resource layouts and timing constraints while maintaining a relatively simple physical routing infrastructure.
Data Source
AI summary
An electronic device includes a plurality of integrated circuits (ICs), each IC comprising an array of resources, and a regional clock circuitry comprising horizontal routing tracks located on each horizontal edge of each of the resources, and vertical routing tracks located on each vertical edge of each of the resources, and a global clock circuitry formed using the horizontal routing tracks and the vertical routing tracks. At least one pair of the horizontal routing tracks located on horizontal IC interface circuitries or the vertical routing tracks located on vertical IC interface circuitries of at least two adjacent ICs of the plurality of ICs are tied together and the global clock circuitry is configured to route a clock signal to each of the plurality of ICs.