Multi-Die Clock Distribution With Reduced Timing Skew

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Solution Overview

Problem

Timing signal skew occurs in circuit devices due to varying distances that timing signals travel to different subcircuits, affecting synchronization and operational efficiency.

Innovation Solution

A hierarchical timing signal distribution network and a method involving the generation of first and second clock signals, where the second clock signal is applied externally if integration occurs, along with conductors to connect timing signal terminals independently, reducing skew between operational circuit nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single clock signal source is used for all subcircuits, then device complexity is reduced, but timing signal skew increases due to varying travel distances

Engineering Contradiction:
Improveclock signal source configurationVSAvoidtiming signal skew
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent divides the clock signal distribution system into multiple independent clock signal sources, each serving specific subcircuits or regions. This segmentation allows each clock source to be optimized for its local area, reducing the varying travel distances that cause timing skew while maintaining manageable device complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If multiple clock signal sources are used to reduce timing skew, then timing precision is improved, but device complexity increases

Engineering Contradiction:
Improvetiming signal skewVSAvoidclock signal source configuration
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements local clock signal sources positioned near specific subcircuits or regions that require precise timing. This local quality approach ensures that timing-critical subcircuits receive clock signals with minimal skew, while other subcircuits can share common clock sources, thereby achieving timing precision where needed without unnecessarily increasing overall device complexity.

Inventive Principle:
Principle #3Local quality

3Productivity

If a hierarchical timing signal distribution network is implemented, then timing signal delivery to multiple nodes is improved, but the network complexity increases

Engineering Contradiction:
Improvetiming signal distribution efficiencyVSAvoiddistribution network structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs a hierarchical timing signal distribution network that organizes clock signal delivery in multiple levels or dimensions. This hierarchical structure efficiently distributes timing signals to numerous operational nodes by breaking down the distribution task into manageable hierarchical levels, improving productivity while controlling network complexity through structured organization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11228316B2Method, system and circuit for multi-die timing signal distribution
Publication Date: 2022.01.18 ARM LTD
  • US11228316B2 patent drawing
  • US11228316B2 patent drawing
  • US11228316B2 patent drawing

AI summary

Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.