Multi-Die Programmable Logic Crossing Circuits for Timing and Congestion
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Solution Overview
Problem
Implementing circuit designs on multi-die programmable devices is challenging due to limited interposers and imposed timing budgets, leading to congestion and reduced crossing frequency, which current design tools cannot automatically address without altering placement and design functionality.
Innovation Solution
A configurable block is introduced, comprising flip-flops and multiplexers, to connect interface blocks to fabric interconnects, allowing for different circuit implementations for inter-die signal crossings, reducing perturbation to existing placement and enabling higher crossing frequencies without additional latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signal crossings between IC dies are increased to implement complex circuit designs, then circuit functionality is improved, but congestion increases and timing constraints are violated due to limited interposers and imposed timing budgets
Solution Approach 1:
The patent segments the signal crossing function into multiple specialized circuits: synchronous crossing circuits for timing-aligned signals, asynchronous crossing circuits for timing-independent signals, and priority-based arbitration circuits. This segmentation allows different types of signals to be handled by appropriate circuits, reducing overall congestion while maintaining circuit functionality.
Solution Approach 2:
The patent introduces intermediary arbitration circuits that mediate between multiple signal sources and limited inter-die crossing resources. These arbitration circuits prioritize signals and manage timing budgets, acting as intermediaries that reduce congestion by efficiently allocating crossing capacity without violating timing constraints.
2Reliability
If timing budget is imposed to guard against PVT variations, then reliability is improved, but crossing frequency is reduced
Solution Approach 1:
The patent employs dynamic timing adjustment mechanisms where timing budgets are adaptively allocated based on actual signal requirements and PVT conditions. Synchronous crossing circuits dynamically align timing based on actual arrival times, while priority arbitration dynamically adjusts timing budgets for different signal types, maintaining reliability while enabling higher crossing frequencies than static timing budgets would allow.
3Manufacturing precision
If manual iteration is performed to optimize signal crossings, then timing and congestion are optimized, but compile time increases
Solution Approach 1:
The patent implements self-service optimization through automated arbitration circuits that autonomously manage signal prioritization and timing allocation without requiring manual iteration. The priority-based arbitration circuits automatically optimize timing and congestion by making real-time decisions based on signal characteristics, eliminating the need for repeated manual compilation and optimization cycles.
4Productivity
If inter-die signal crossings are implemented at high frequency, then productivity is improved, but timing constraints are violated due to PVT variations
Solution Approach 1:
The patent segments high-frequency signal crossings into synchronous and asynchronous paths. Synchronous circuits handle timing-critical signals with dynamic timing alignment, while asynchronous circuits handle less time-sensitive signals with priority arbitration. This segmentation enables high-frequency operation while maintaining timing constraint satisfaction through appropriate circuit selection.
Solution Approach 2:
The patent changes timing parameters dynamically based on signal type and PVT conditions. Priority arbitration circuits adjust timing budgets and crossing frequencies in real-time, allowing high-frequency operation for asynchronous signals while maintaining strict timing constraints for synchronous signals, thus achieving both high productivity and reliability.
Data Source
AI summary
In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.