Multi-Die Interconnect Layout Using Edge Routing for Lower Signal Delay
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Solution Overview
Problem
Conventional chip packaging technologies face challenges in reducing data signal transmission delay between dies in a single package, particularly for sensitive pairs of dies, due to complex routing and significant signal interference, which affects data transmission efficiency.
Innovation Solution
The solution involves interconnecting non-adjacent dies through routing in an edge area outside the bounding box on the interconnect layer, while adjacent dies are interconnected within the bounding box area, thereby reducing signal interference and transmission delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dies are interconnected through routing in the bounding box area, then routing complexity increases and signal interference occurs, but data signal transmission delay is large
Solution Approach 1:
The patent extends routing from the traditional two-dimensional bounding box area to a three-dimensional space by utilizing the edge area outside the bounding box. This dimensional expansion allows routing paths to go around而非 through the crowded central area, reducing signal interference and transmission delay while maintaining routing organization.
Solution Approach 2:
The patent segments the routing area into two distinct zones: the bounding box area for general routing and the edge area for high-performance critical paths. This segmentation allows different routing strategies to be applied to different functional requirements, with the edge area providing dedicated low-interference paths for time-sensitive signals.
2Adaptability or versatility
If more dies are integrated in a single package, then device functionality increases, but signal interference and transmission delay increase
Solution Approach 1:
As more dies are integrated in the package, the patent utilizes the edge area surrounding the bounding box to provide additional routing dimensions. This allows signal paths to extend outward rather than competing for space within the crowded central area, maintaining low transmission delay even as die count increases.
Solution Approach 2:
The patent pre-allocates edge area routing resources for high-performance communication paths before die integration is completed. This preliminary preparation ensures that as more dies are added to the package, dedicated low-interference paths are already available, preventing signal interference from increasing with die count.
3Reliability
If routing is performed in the bounding box area, then interconnection is achieved, but signal interference and transmission delay are significant
Solution Approach 1:
The patent extracts critical high-performance routing paths from the crowded bounding box area and places them in the edge area. This separation removes time-sensitive signals from the harmful electromagnetic environment of the central routing area, reducing signal interference and improving transmission reliability for critical communications.
Solution Approach 2:
The edge area acts as an intermediary zone between the bounding box routing area and the external package environment. It provides a buffer region with lower signal interference for critical communications, mediating between the high-density internal routing and the requirements for low-interference high-speed data transmission.
Data Source
Figure 1a~1b
Figure 2a~2b
Figure 2c~3a
AI summary
This application provides a chip (100), and the chip (100) includes an interconnect layer (110) and a plurality of dies disposed on the interconnect layer (110). The plurality of dies include a first die (1) and a second die (2), the first die (1) and the second die (2) are interconnected through direct routing in an edge area, the edge area is an area outside a bounding box on the interconnect layer (110), and the bounding box is a peripheral boundary of the plurality of dies on the interconnect layer (110). Because there is no signal routing in the edge area on the interconnect layer (110), and the edge area is not interfered with by another data signal, the first die (1) and the second die (2) are interconnected through routing in the edge area. In this way, a delay of data signal transmission between the two dies can be reduced, and data transmission efficiency can be improved.