Multi-Die Memory ESD Clamp Isolation for Peak Current Reduction
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Solution Overview
Problem
Multi-die semiconductor devices face challenges in managing peak current levels and overall current consumption, particularly during power-on modes, due to the interaction between active driver circuits and ESD power clamp circuits, which can lead to performance degradation and increased power consumption.
Innovation Solution
The semiconductor device configuration includes a substrate with multiple memory dies, where ESD power clamp circuits are electrically disconnected from the substrate interface, reducing peak current levels and standby current consumption by isolating ESD clamp circuits, thereby optimizing package-level configurability and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD power clamp circuits are connected to substrate interface in multi-die semiconductor devices, then electrostatic discharge protection is provided, but peak current levels and overall current consumption increase during power-on modes
Solution Approach 1:
The patent implements dynamic control of ESD power clamp circuits by selectively enabling or disabling specific ESD clamp circuits based on operational conditions. The controller adjusts which ESD protection circuits are active during different power-on modes, allowing the system to maintain necessary ESD protection while minimizing current consumption by keeping unnecessary ESD clamps disabled.
Solution Approach 2:
The system changes the operational parameters of ESD power clamp circuits by controlling their enable/disable states. Different subsets of ESD clamp circuits are activated depending on the power-on mode, effectively changing the electrical configuration to balance protection needs against current consumption constraints.
2Reliability
If multiple ESD power clamp circuits are activated in parallel, then ESD protection coverage is improved, but peak current levels during power-on increase significantly
Solution Approach 1:
The patent divides the ESD protection function into multiple independent ESD power clamp circuits, each controllable separately. Instead of activating all ESD clamps simultaneously, the controller segments their activation based on which ones are necessary for the current operational mode, thereby providing adequate ESD protection coverage while avoiding the cumulative peak current of full parallel activation.
Solution Approach 2:
The system applies partial action by activating only the necessary subset of ESD power clamp circuits rather than all available circuits. This provides sufficient ESD protection for the given operational context without the excessive current consumption that would result from activating every ESD clamp in parallel.
3Adaptability or versatility
If all contact pads are electrically connected to substrate contacts, then maximum electrical connectivity is achieved, but current consumption and device complexity increase
Solution Approach 1:
The patent implements dynamic electrical connectivity by using switches or controllable connections between contact pads and substrate contacts. The controller dynamically adjusts which contact pads are electrically connected based on the operational requirements, enabling the system to achieve maximum connectivity when needed while reducing complexity and current consumption during other modes.
Solution Approach 2:
The contact pad structure is designed with multi-functionality, where the same physical contact pad infrastructure can serve different purposes depending on configuration. By controllably connecting or disconnecting contact pads from substrate contacts, the system achieves universal adaptability across different operational modes without requiring separate dedicated connections for each function.
Data Source
AI summary
A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.