Multi-Die FPGA Package Layout for Shorter Interconnect Routing
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Solution Overview
Problem
The complexity of long routes and added redrivers/flip-flops in routing paths of FPGA dies negatively impacts overall FPGA performance, limiting the development and manufacturing of high-density FPGA devices.
Innovation Solution
An integrated circuit module with multiple field-programmable gate array (FPGA) dies configured to function as a single entity, utilizing a substrate for side-by-side placement and inter-die communication through serializers and deserializers to enhance signal transmission and user-defined logic functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If FPGA die density is increased, then more logic functions can be integrated, but routing complexity and performance degradation increase due to long routes and added redrivers/flip-flops
Solution Approach 1:
The patent divides a large-density FPGA into multiple smaller FPGA dies, each with its own logic blocks and routing resources. These smaller dies are then interconnected through the substrate to form a functional equivalent of a single large FPGA, thereby avoiding the routing complexity issues associated with high-density single-die designs.
Solution Approach 2:
The patent transitions from a two-dimensional single-die architecture to a three-dimensional multi-die stacked architecture. By stacking multiple FPGA dies vertically and connecting them through substrate pads and inter-die routing, the system achieves high density without the routing complexity of planar high-density designs.
2Quantity of substance
If FPGA die density is increased, then more logic functions can be integrated, but performance deteriorates due to long routing paths and additional redrivers/flip-flops
Solution Approach 1:
By segmenting the FPGA into multiple smaller dies, each die maintains compact internal routing paths with fewer redrivers and flip-flops, preserving signal integrity and performance. The segmentation allows logic functions to be distributed across dies with optimized local routing.
Solution Approach 2:
The substrate acts as an intermediary between multiple FPGA dies, providing dedicated high-speed inter-die connection paths. These substrate-mediated connections enable direct routing between dies without requiring long paths through individual die routing resources, thereby maintaining performance.
3Quantity of substance
If multiple FPGA dies are interconnected, then high-density functionality is achieved, but device complexity increases
Solution Approach 1:
The substrate pads are designed with multi-functionality, serving both as I/O interfaces for external connections and as inter-die connection points. This universal design simplifies the interconnection architecture by using the same physical infrastructure for multiple purposes.
Solution Approach 2:
The patent merges multiple FPGA dies into a unified functional entity through the substrate interconnection network. The dies are combined such that they operate as a single high-density FPGA, with the substrate serving as the merging medium that integrates logic blocks, routing resources, and I/O interfaces across dies.
Data Source
AI summary
An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.