Wafer-Level Multi-Die Interconnect Layout for Gap Space Utilization
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Solution Overview
Problem
Conventional semiconductor fabrication methods leave significant wasted space between IC dies on a wafer, which could be utilized to enhance functionality or versatility, but current methods do not efficiently utilize this space.
Innovation Solution
The implementation of wafer-level structures with interconnected IC dies and dual seal rings that surround the dies, along with the formation of conductive elements and other structures in the gap regions to electrically interconnect the dies and improve chip area utilization, allowing for enhanced performance and functionality without the need for additional design and fabrication resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional fabrication methods are used, then IC dies can be manufactured with standard processes, but significant wasted space remains between the dies on the wafer
Solution Approach 1:
The patent merges previously separate functional elements (interconnection structures, test structures, alignment marks) into the gap regions between dies. By forming these elements within the inter-die spaces rather than within individual dies or as separate wafer-level structures, the invention combines multiple functions into the previously wasted space, thereby increasing chip area utilization without requiring additional fabrication resources.
2Adaptability or versatility
If additional functional elements are added to enhance versatility, then device functionality improves, but design and fabrication complexity increases
Solution Approach 1:
The gap regions between dies are designed to serve multiple functions simultaneously: providing electrical interconnections between adjacent dies, containing test structures for die validation, incorporating alignment marks for lithography registration, and offering mechanical support. This multi-functional approach enhances device versatility without proportionally increasing design and fabrication complexity, as all these elements are formed using the same fabrication processes that would otherwise be performed separately.
Data Source
AI summary
An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.