Multi-Die IC Package Segmentation for Pad-Limited Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The transition to smaller nanometer technologies in silicon processing leads to pad-limited designs, where digital logic cannot be implemented as densely due to the shrinkage of analogue and IO cells, and introduces a dichotomy between low voltage, high speed input/output logic and higher voltage interconnect technologies, making it difficult to port high speed analogue interfaces and requiring incompatible transistor gate oxide thicknesses.
Innovation Solution
A package comprising multiple dies with a communication channel allowing for high bandwidth and low latency, decoupling analogue and digital blocks, enabling different voltage and transistor gate oxide thicknesses for each die, and using a common interface to simplify modification and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the feature size in silicon technology is decreased, then digital logic area is reduced, but pad-limited design occurs where analogue and IO cells cannot shrink
Solution Approach 1:
The patent divides the system into multiple separate dies, each optimized for specific functions (analogue, digital logic, IO). This segmentation allows each die to be designed independently with appropriate feature sizes, avoiding the pad limitation that occurs when all components must share a common interconnect layer in a single-die architecture.
2Speed
If low voltage, high speed input/output logic is implemented, then high performance is achieved, but incompatible transistor gate oxide thicknesses are required
Solution Approach 1:
The patent separates different voltage domains and interface technologies onto different dies. Each die can be manufactured with optimized gate oxide thickness for its specific voltage requirement, eliminating the manufacturing conflict that arises when multiple incompatible thicknesses must be supported within a single die.
Solution Approach 2:
The patent introduces an intermediary interface layer between different dies that handles the voltage translation and signal conditioning. This intermediary allows low voltage high-speed logic to interface with higher voltage interconnect technologies without requiring all components to use the same gate oxide thickness.
3Productivity
If high speed analogue interfaces are ported to new process, then modern technology is utilized, but significant time and expert attention are consumed
Solution Approach 1:
The patent isolates analogue interfaces on separate dies that can be designed and tested independently before integration. This segmentation allows the analogue interface design to be optimized for the new process without requiring extensive rework of the entire system, reducing the time and expertise needed for porting.
Data Source
Figure 1a
Figure 1b
Figure 2
AI summary
A package comprising a first die; a second die; an interface between the first and second die, said interface being configured to transport a plurality of control signals, wherein the number of control signals is greater than a width of said interface, and at least one of said first and second dies comprising configurable grouping means for providing a plurality of groups of control signals whereby a group of signals is transmitted across the interface together.