Multi-Die IC Power Management with Standby State Retention
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Solution Overview
Problem
Conventional power management in FPGAs, where a host IC chip is used to disable power, results in issues such as loss of state upon waking up, verification challenges for multiple IC interactions, and unnecessary active controller states, as well as problematic power-down requirements for shared circuits.
Innovation Solution
A packaged multi-die integrated circuit architecture where a first die manages power for a second die, allowing for efficient transition between operational and standby modes, with selective power supply and state retention, using a CPLD or smart memory for power management and voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a host IC chip is used to disable power for FPGA hibernate mode, then power consumption is reduced, but state is lost upon waking up and verification complexity increases
Solution Approach 1:
The patent merges the power management functionality with the FPGA device itself by integrating a power management unit within the same IC package. This eliminates the need for a separate host IC chip to control power, thereby reducing verification complexity while maintaining power savings. The power management unit is directly coupled to the FPGA's power supply circuitry, enabling localized control without requiring inter-chip communication verification.
2Loss of energy
If a host IC chip is used to control FPGA power state, then power management is achieved, but additional active controller states are required
Solution Approach 1:
The patent extracts the power management control logic from the host IC chip and integrates it directly into the FPGA package. The power management unit is implemented as a dedicated circuit within the same package that directly controls the power supply to the FPGA, eliminating the need for additional active controller states in a separate host chip. This reduces the overall system complexity while maintaining efficient power management.
3Adaptability or versatility
If multiple IC chips are used in the design, then functionality is enhanced, but interaction verification becomes problematic
Solution Approach 1:
The patent combines the power management functionality with the FPGA in the same IC package, eliminating the need for separate host IC chips. This merging reduces the number of inter-chip interactions that require verification, while the packaged multi-die architecture maintains enhanced functionality through integrated power management and FPGA cores.
4Loss of energy
If circuits sharing power plane are powered down with FPGA, then power consumption is reduced, but operational flexibility is lost
Solution Approach 1:
The patent implements local quality by providing independent power control for the FPGA and its associated circuits through the integrated power management unit. Each circuit can be selectively powered on or off based on operational requirements, allowing different parts of the system to have different power states simultaneously. This enables operational flexibility while maintaining power savings, as circuits sharing the power plane do not need to be uniformly powered down.
Data Source
AI summary
Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.