Multi-Die Latency Measurement via Clock Phase Observation
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Solution Overview
Problem
Existing methods for measuring data bit latency across multiple FIFO buffers on separate semiconductor dies are insufficient due to uncertainty introduced by phase relationships caused by relative clock insertion delays, which are not adequately accounted for in determining accurate latency.
Innovation Solution
The implementation of observation circuits on each semiconductor die to measure phase delay differences and insertion delays between write and read clocks, along with sampling clock insertion delays, allows for the adjustment of base latencies to achieve more accurate latency measurements across multiple FIFO buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If base latency of FIFO buffers is measured using average occupancy method, then measurement simplicity is maintained, but measurement precision deteriorates due to unaccounted phase delay differences from clock insertion delays
Solution Approach 1:
The latency measurement is segmented into multiple components: base latency from average occupancy, phase delay difference between write and read clocks, and insertion delay of sampling clock. Each component is measured separately using dedicated observation circuits that sample clock signals at different points in the FIFO buffer, then combined to achieve precise total latency measurement.
Solution Approach 2:
Observation circuits serve as intermediary elements that sample and compare clock signals at different stages of the FIFO buffer. These circuits measure phase delay differences and insertion delays, acting as mediators between the clock distribution system and the latency calculation logic, enabling accurate compensation for clock timing variations.
2Reliability
If clock insertion delays are not measured and compensated, then device complexity remains low, but reliability deteriorates due to uncertainty in phase relationships between clocks on separate dies
Solution Approach 1:
The observation circuits provide feedback information about phase delay differences and insertion delays to the latency calculation logic. This feedback enables dynamic compensation for clock timing variations, ensuring reliable latency measurement and timestamp generation despite variations in clock insertion delays across different semiconductor dies.
Solution Approach 2:
Phase delay differences and insertion delays are measured and compensated for in advance before actual latency calculation. The observation circuits continuously monitor clock signals and pre-compute correction values that are applied to the base latency measurement, ensuring accurate results without adding complexity to the core FIFO operation.
3Measurement precision
If observation circuits sample clock signals to measure phase delay differences, then latency accuracy improves, but loss of time increases due to additional measurement and adjustment operations
Solution Approach 1:
The observation circuits continuously sample clock signals and measure phase delay differences without interrupting the normal FIFO operation. The latency measurement and compensation process operates in parallel with data transfer, eliminating the need for separate measurement cycles and minimizing time loss while maintaining continuous accurate latency tracking.
Data Source
AI summary
Circuitry and methods are disclosed for accurately measuring a latency of a data path through multiple FIFO buffers on separate semiconductor dies. A base latency of each FIFO may be measured by measuring an average occupancy of the FIFO. The base latency of each FIFO may then be adjusted using quantities measured using the circuitry and methods disclosed herein. These quantities may include: the phase delay difference between FIFO read and write clocks; and the insertion delay for the FIFO read clock. Furthermore, an insertion delay difference of the sampling clock between the separate dies may be measured and used to adjust these quantities. Other embodiments and features are also disclosed.