Multi-Die Package Lateral Adjacency for Thermal and Bandwidth Management
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Solution Overview
Problem
Conventional integrated circuit packaging faces challenges in minimizing package size, improving inter-die communication, and providing effective cooling, due to limited space for stiffeners and cooling mechanisms, as well as restricted communication paths through low-pitch interconnects in stacked die configurations.
Innovation Solution
The solution involves using separate core and uncore dies with varying minimum pitches, where the core die is manufactured using a smaller node (e.g., 14 nm) and the uncore die using a larger node (e.g., 22 nm or 32 nm), with the uncore die acting as a high-bandwidth bridge between the core and memory dies, and incorporating features like underfill materials, metal stiffeners, and thermal solutions such as heat sinks or heat pipes to enhance mechanical stability and cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If discrete logic and memory BGA packages are stacked vertically (PoP configuration), then component density is increased, but package thickness is reduced and space for cooling mechanisms is limited
Solution Approach 1:
The patent transitions from a conventional vertical PoP stacking arrangement to a lateral adjacency configuration where logic die and memory die are positioned side-by-side on the same substrate. This dimensional reorganization eliminates the need for vertical stacking, thereby increasing package thickness and creating available space for integrating cooling mechanisms such as heat sinks and thermal vias without compromising component density.
2Quantity of substance
If discrete logic and memory BGA packages are stacked vertically (PoP configuration), then component density is increased, but communication paths are restricted to low-pitch interconnects
Solution Approach 1:
By repositioning logic die and memory die from vertical stacking to lateral adjacency on the substrate, the patent enables the implementation of high-speed communication interfaces such as CXL (Compute Express Link) that operate in the lateral plane. This configuration allows for higher pitch interconnects and improved signal integrity, thereby increasing communication bandwidth between logic and memory components while maintaining high component density through optimized substrate layout.
3Volume of stationary object
If package size is minimized through vertical stacking, then space is reduced, but space for stiffeners and cooling mechanisms is limited
Solution Approach 1:
The patent adopts a lateral adjacency layout instead of vertical stacking, which increases package thickness and creates vertical space for integrating stiffeners for mechanical support and cooling mechanisms such as heat sinks, thermal vias, and heat spreaders. This dimensional change allows the package to maintain a compact footprint while accommodating necessary mechanical and thermal management components, thereby reducing overall device complexity despite the increased thickness.
4Ease of manufacture
If core die uses smaller node (e.g., 14 nm) and uncore die uses larger node (e.g., 22 nm or 32 nm), then manufacturing cost is reduced, but pitch variation between dies must be managed
Solution Approach 1:
The patent implements a heterogeneous multi-die package where the core logic die is fabricated using a smaller process node (e.g., 14 nm) for high-performance computing functions, while the uncore logic die and memory die are fabricated using larger process nodes (e.g., 22 nm or 32 nm) for lower-cost, less performance-critical functions. The substrate design incorporates pitch adaptation mechanisms such as re-pitching layers, via arrays, and interconnect routing that accommodate the different pitch requirements of dies manufactured at different nodes, thereby enabling cost-effective manufacturing while maintaining manufacturing precision through localized pitch management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces package thickness, increases communication bandwidth, and provides adequate cooling while maintaining mechanical stability, resulting in a more efficient and compact packaging architecture with improved yield and manufacturing cost-effectiveness.
Implementation Method 1
The system includes underfill material between the first die and the substrate
Implementation Method 2
at least one of a metal stiffener, a heat sink, and a heat tube is on the first die
Implementation Method 3
at least one of a metal stiffener, a heat sink, and a heat tube is on the first die
Implementation Method 4
at least one of a metal stiffener, a heat sink, and a heat tube is on the first die
Implementation Method 5
at least one of a metal stiffener, a heat sink, and a heat tube is on the first die
Data Source
AI summary
An embodiment includes an apparatus comprising: a substrate; a first die including a processor core; a second die not including a processor core; and a third die including memory cells; wherein: (a)(i) the first die has a smaller minimum pitch than the second die; (a)(ii) a first vertical axis intersects the substrate and the first and second dies but not the third die; and (a)(iii) a second vertical axis intersects the substrate and the second and third dies but not the first die. Other embodiments are described herein.