Multi-Die Memory Interface Layout for High Bandwidth at Lower Power
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Solution Overview
Problem
The increasing demand for higher performance and capacity in DRAM devices leads to significant power consumption challenges, making it difficult to advance signaling rate and capacity while conventional DRAM fabrication processes compromise on efficiency due to inefficient high-speed logic circuitry.
Innovation Solution
A multi-die memory device architecture is introduced, where high-speed interface and core storage functions are split between separate integrated circuit dice, with the interface die fabricated using a process for power-efficient high-speed circuitry and the storage die using a process that balances cell retention time and storage density, allowing for shorter bit lines and reduced access power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM devices increase signaling bandwidth and storage capacity, then performance and capacity improve, but power consumption increases dramatically
Solution Approach 1:
The patent divides the memory device into multiple independent memory dies (first memory die, second memory die, etc.), each capable of independent operation. This segmentation allows the system to achieve higher aggregate bandwidth by activating multiple dies simultaneously while managing power consumption by selectively enabling only the required number of dies based on demand, thus resolving the contradiction between bandwidth and power consumption.
2Quantity of substance
If DRAM devices increase storage capacity, then capacity improves, but power consumption increases dramatically
Solution Approach 1:
The patent divides the memory device into multiple independent memory dies (first memory die, second memory die, etc.), each capable of independent operation. This segmentation allows the system to achieve higher aggregate bandwidth by activating multiple dies simultaneously while managing power consumption by selectively enabling only the required number of dies based on demand, thus resolving the contradiction between bandwidth and power consumption.
3Ease of manufacture
If conventional DRAM fabrication processes are used, then manufacturing simplicity is maintained, but high-speed logic circuitry efficiency is compromised
Solution Approach 1:
The patent separates the memory array functions (implemented using conventional DRAM fabrication processes on memory dies) from the high-speed interface logic functions (implemented on separate interface dies or integrated on the same package). This allows each component to be optimized for its specific function while maintaining ease of manufacture through established processes.
4Speed
If multiple memory dies are integrated in close proximity, then data retrieval speed improves through shorter bit lines, but device complexity increases
Solution Approach 1:
The patent combines multiple memory dies and interface logic into a single integrated memory device package with unified control logic that manages multiple dies. This merging approach simplifies the overall system architecture by providing centralized control while maintaining the speed benefits of short internal bit lines, thus resolving the contradiction between speed and complexity.
Data Source
AI summary
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.