Multi-Die Memory Impedance Calibration for Signal Integrity
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Solution Overview
Problem
As semiconductor memory devices operate at increased speeds, signal swing widths decrease, making them susceptible to distortion due to impedance mismatch caused by process, voltage, and temperature variations, which can degrade power integrity and cause electro-magnetic interference.
Innovation Solution
A semiconductor memory device with multiple dies communicates through impedance pads, utilizing a master die to perform an impedance calibration operation, which is sequentially followed by slave dies, using an external resistor to set output driver resistances and reference voltages, thereby limiting interference and maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of semiconductor memory devices is increased, then the productivity is improved, but the signal swing width decreases making signals more susceptible to distortion due to impedance mismatch
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the output impedance of driver circuits and termination impedance of receiver circuits based on detected signal characteristics. The impedance calibration circuit measures the actual signal swing width and adjusts impedance parameters (resistance values) to optimize signal quality at high operating speeds, resolving the contradiction between speed and signal integrity.
Solution Approach 2:
The patent implements feedback mechanisms where the impedance calibration circuit continuously monitors signal swing width and impedance mismatch conditions, then feeds this information back to adjust the output driver impedance and termination impedance. This closed-loop feedback system maintains signal integrity even as operating speed increases, preventing the degradation that would normally occur at higher frequencies.
2Reliability
If impedance calibration operations are performed to adjust output impedance and termination impedance, then the signal distortion is reduced, but the device complexity increases due to additional calibration circuits and operations
Solution Approach 1:
The patent merges the impedance calibration function with the existing output driver and receiver circuits. The impedance calibration circuit is integrated into the memory device architecture, sharing physical resources and control logic with normal operation circuits. This consolidation reduces the overall device complexity compared to having separate, dedicated calibration systems, while still achieving effective impedance matching.
Solution Approach 2:
The impedance calibration system operates autonomously within the memory device, automatically detecting impedance mismatch conditions and adjusting its own parameters without requiring external intervention. The calibration circuits self-test and self-adjust the output driver and receiver impedance, eliminating the need for complex external calibration equipment or manual adjustment mechanisms.
3Reliability
If multiple memory dies communicate through impedance pads using sequential impedance calibration, then the power integrity is maintained and electro-magnetic interference is reduced, but the calibration time increases due to sequential operations
Solution Approach 1:
The patent performs impedance calibration as a preliminary action during the initialization phase before normal memory operations begin. The master die completes its impedance calibration first, establishing a reference state, then slave dies perform their calibrations in sequence. By completing all impedance calibrations before data transmission starts, the system ensures optimal signal quality from the outset without incurring time penalties during active operation.
Solution Approach 2:
The impedance calibration is implemented as a periodic initialization routine that occurs at defined intervals or system startup. The master die triggers calibration cycles, and slave dies respond in sequence during designated calibration periods. This periodic structure allows the system to maintain power integrity through regular impedance optimization while confining the time-consuming sequential calibration operations to specific time windows rather than continuous operation.
Data Source
AI summary
A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.