Multi-Die Package Stacked MOSFETs Reduce Rdson
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOSFET switching circuits face challenges in maximizing die area to minimize drain-to-source on resistance (Rdson) without increasing the overall size of the circuit, particularly due to the constraints of co-packaging high side and low side MOSFETs.
Innovation Solution
A multi-die package configuration where first and second semiconductor dies are bonded in superimposition, with each die having gate, drain, and source regions, and a floating metal layer acting as both a die pad and bonding pad, allowing for larger die areas and reduced Rdson within the same package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOSFETs are co-packaged side by side on separate die pads, then the package size is reduced, but the die area is constrained and Rdson cannot be minimized
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side die arrangement to a three-dimensional stacked configuration. Multiple dies are arranged vertically in layers rather than horizontally adjacent, allowing each die to achieve larger area without increasing the package footprint. This dimensional change resolves the contradiction by decoupling die area from package area.
Solution Approach 2:
The patent implements a stacked die structure where multiple semiconductor dies are nested vertically within the same package footprint. Each die is positioned in a different layer along the vertical axis, allowing maximum utilization of the package volume while maintaining a compact footprint, thus enabling larger die areas without increasing package size.
2Area of moving object
If die area is increased to minimize Rdson, then the package size must be increased, but the circuit size constraint is violated
Solution Approach 1:
By stacking dies vertically in multiple layers, the patent enables each die to have a larger area while the overall package footprint remains constant. The vertical dimension provides additional space that allows increased die area without expanding the horizontal package dimensions, thus resolving the contradiction.
Solution Approach 2:
The patent employs asymmetric die stacking where dies of different sizes and functions are arranged in specific vertical configurations. This asymmetric arrangement optimizes the use of available vertical space, allowing larger die areas for power devices while maintaining a compact package footprint through strategic positioning of different die sizes in the stack.
Data Source
AI summary
A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.