Multi-Die IC Package Structure With Dielectric-Embedded Connectors
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Solution Overview
Problem
Existing methods for packaging integrated circuits (ICs) in multi-chip modules often result in large package footprints and high costs, particularly when using stacked approaches or through silicon vias.
Innovation Solution
A method and structure for packaging multiple ICs in a stacked arrangement, where a primary IC die is paired with a secondary IC die of smaller area, connected via electrical connectors and an intermediate dielectric or insulating layer, eliminating the need for through-silicon vias and maintaining a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked approaches or through silicon vias are used for multi-chip packaging, then electrical connectivity between dies is achieved, but package footprint increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from planar side-by-side die arrangement to a stacked three-dimensional configuration, connecting dies vertically through the substrate rather than horizontally. This dimensional change enables multiple dies to be packaged in a smaller footprint area while maintaining electrical connectivity through vertical interconnects.
Solution Approach 2:
The patent embeds multiple dies within a single package substrate in a nested configuration, where smaller dies are positioned on or within the larger package structure. This nesting approach allows multiple functional units to be integrated into a compact package footprint while maintaining access to all die surfaces for electrical connections.
2Reliability
If through silicon vias are used for die interconnection, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the complex through-silicon via formation process from the manufacturing approach. Instead of creating vertical vias through the substrate, the design uses surface-mounted connections and routed traces on the substrate surface, eliminating the need for costly TSV fabrication processes while maintaining electrical connectivity between stacked dies.
Solution Approach 2:
The patent employs standard substrate routing and surface-mount technology rather than expensive through-silicon via structures. This approach uses more conventional, cost-effective manufacturing processes that are already widely implemented in the industry, reducing overall package cost while achieving the same electrical interconnection function.
3Reliability
If multiple dies are placed side-by-side on an interposer, then electrical connectivity is achieved, but package footprint increases
Solution Approach 1:
The patent transitions from planar side-by-side die arrangement to a stacked three-dimensional configuration, connecting dies vertically through the substrate rather than horizontally. This dimensional change enables multiple dies to be packaged in a smaller footprint area while maintaining electrical connectivity through vertical interconnects.
Data Source
AI summary
This application describes electronic circuit packages and methods of manufacture. The package (100, 300) includes a primary integrated circuit die (101) with a smaller secondary integrated circuit die (102) attached to a first surface of the primary integrated circuit die in a first location. A first set of electrical connectors (103) extend from the first surface of the primary integrated circuit die outside the first location to a package connection layer (106) to provide electrical connection between the package connection layer and the primary integrated circuit die. An intermediate layer (108) of dielectric or insulating material extends between the primary integrated circuit die and the package connection layer so that the dielectric or insulating material surrounds the first set of electrical connectors and there is at least some dielectric or insulating material between the second integrated circuit die and the package connection layer.