Multi-Die IC Package with Interrupt Processing Interface
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Solution Overview
Problem
The transition to smaller nanometer technologies in silicon processing leads to challenges such as pad-limited designs, incompatibility between low voltage high-speed IO logic and higher voltage interconnect technologies, and resource-intensive porting of high-speed analog interfaces, resulting in inefficient digital logic implementation and increased design complexity.
Innovation Solution
A package comprising multiple dies with a common interface that decouples analog and digital blocks, allowing each die to operate with different voltage and transistor gate oxide thicknesses, and utilizing a universal communication channel for high bandwidth and low latency inter-die communication, enabling modular design and reduced design time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size in silicon technology is decreased to shrink digital logic, then digital logic area is reduced, but analog and IO cells shrink less leading to pad-limited designs
Solution Approach 1:
The patent divides the system into separate dies - one die for digital logic and another die for analog/IO functions. This segmentation allows each die to be optimized independently for its specific function, enabling digital logic to shrink while analog cells maintain their required sizes without pad limitations constraining the overall design.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture where digital and analog blocks are separated onto different dies stacked vertically. This dimensional change allows independent optimization of each die type without the pad layout constraints that would otherwise limit design flexibility.
2Adaptability or versatility
If low voltage high-speed IO logic is integrated with higher voltage interconnect technologies, then functional integration is improved, but incompatibility between voltage requirements arises
Solution Approach 1:
The patent separates low voltage high-speed IO logic onto one die and higher voltage interconnect technologies onto another die. This segmentation eliminates voltage compatibility issues by allowing each die to operate at its optimal voltage level independently, while the interface between dies handles the voltage translation.
Solution Approach 2:
The patent introduces an interface layer between the separate dies that acts as an intermediary, handling voltage level translation and signal conditioning. This intermediary enables compatible communication between components with different voltage requirements without compromising reliability.
3Reliability
If high-speed analog interfaces are ported to new processes, then interface functionality is maintained, but resource consumption and design time increase
Solution Approach 1:
The patent uses standardized interface blocks that can be copied and reused across different process nodes. These pre-characterized interface templates maintain functionality while eliminating the need for resource-intensive re-porting and re-validation, significantly reducing design time for new process implementations.
Solution Approach 2:
The patent creates universal interface blocks that are designed to work across multiple process technologies. These multi-functional interface components can be instantiated repeatedly in different contexts without requiring process-specific customization, reducing both resource consumption and design time.
4Device complexity
If multiple dies are integrated in a package with common interface, then design complexity is reduced, but inter-die communication overhead is introduced
Solution Approach 1:
The patent merges multiple communication functions (data transfer, interrupt signaling, status reporting) into a unified inter-die interface protocol. This consolidation reduces the number of separate communication channels needed and optimizes the overall communication efficiency, minimizing latency despite the physical separation of dies.
Solution Approach 2:
The patent implements continuous data transfer mechanisms between dies, including buffered interfaces and pipelined communication protocols. These mechanisms maintain continuous useful action across the die boundary, reducing the impact of communication latency on overall system performance.
Data Source
AI summary
A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.