Multi-die Package with Segmented Pads for Scalable Memory
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Solution Overview
Problem
Current semiconductor packaging technologies that integrate processor and DRAM in a single package face limitations in scalability, as the DRAM capacity cannot be easily expanded, leading to increased design and manufacturing costs due to the need for multiple chip designs for varying DRAM requirements.
Innovation Solution
A multi-die package architecture that includes a main die with a memory controller and multiple sets of pads, coupled with a memory die and additional pins, allowing for the expansion of DRAM capacity by connecting an external memory chip, thereby enhancing scalability and reducing design costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If processor and DRAM are integrated in a single package, then traces and pads on PCB are reduced, but DRAM capacity cannot be expanded and design costs increase
Solution Approach 1:
The memory interface is segmented into multiple independent pad sets (first set, second set, third set of pads) on the main die. The first set connects to an internal memory die, while the second and third sets connect to external memory chips. This segmentation allows the system to flexibly configure memory capacity by combining different memory components without redesigning the entire package, thus maintaining PCB area reduction while enabling DRAM capacity expansion.
Solution Approach 2:
The main die is designed with multiple pad sets that serve different functions: the first set interfaces with an internal memory die, while the second and third sets interface with external memory chips. This multi-functional design allows a single package to support various memory capacity configurations by selectively connecting different memory components, making the package adaptable to different DRAM capacity requirements without increasing PCB area.
2Adaptability or versatility
If multiple chips are designed for different DRAM capacities, then DRAM capacity requirements are met, but design and manufacturing costs increase
Solution Approach 1:
A single multi-die package design incorporates multiple pad sets that can be configured to support different DRAM capacity requirements by selectively connecting internal and external memory chips. This universal design eliminates the need to create multiple separate chip designs for different capacities, thereby reducing design complexity and manufacturing costs while maintaining adaptability to various memory requirements.
Solution Approach 2:
The package design incorporates dynamic configurability through multiple pad sets that can be selectively activated or connected to different memory components based on the specific application requirements. This dynamic configuration capability allows the same package to adapt to different DRAM capacity needs without requiring separate manufactured chips, thus reducing design and manufacturing costs.
Data Source
AI summary
The present invention provides a multi-die package including main die, a memory die, a first set of pins and a second set of pins. The main die includes a memory controller, a first set of pads, a second set of pads and a third set of pads. The memory die is coupled to the first set of pads and the second set of pads of the main die. The first set of pins is coupled to the third set of pads of the main die. The second set of pins is coupled to the second set of pads of the main die. The memory controller accesses the memory die through the first set of pads and the second set of pads, and the memory controller accesses a memory chip external to the multi-die package through the second set of pads and the third set of pads.