Multi-Die Package Stacking for Compact Low-Parasitic Power ICs
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Solution Overview
Problem
The increasing demand for compact and efficient power supply systems in portable electronics poses a challenge due to the high fabrication costs of monolithic dies, which require 18-20 masks for CMOS controllers and 8-9 masks for DMOS FETs, making it costly to integrate these components.
Innovation Solution
A multi-die package structure comprising an embedded die, a flip chip die, and an attached die, where the embedded die is embedded in a substrate, the flip chip die is mounted above the substrate, and the attached die is bonded to the flip chip die, allowing for different fabrication processes for each die and reducing overall costs through co-packing and efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If monolithic die is used to integrate FETs and controllers, then device functionality is improved, but fabrication cost increases significantly
Solution Approach 1:
The patent divides the monolithic die into separate dies: a first die for FETs and a second die for controllers. Each die can be fabricated using its own optimized process (DMOS for FETs, CMOS for controllers), avoiding the high cost of integrating both on a single die while maintaining full functionality through package-level integration.
2Ease of manufacture
If multiple separate dies are used, then fabrication cost is reduced, but package size increases
Solution Approach 1:
The patent embeds the first die (FETs) into the substrate and places the second die (controllers) above it, with the third die attached onto the second die. This nested vertical arrangement allows multiple dies to occupy overlapping footprint areas, significantly reducing the overall package size compared to a planar side-by-side layout while enabling each die to be fabricated separately.
3Adaptability or versatility
If separate dies are co-packed, then fabrication flexibility is improved, but parasitic resistance and inductance increase
Solution Approach 1:
The patent transitions from planar lateral connections to vertical three-dimensional interconnections by embedding one die in the substrate and stacking other dies above it. This vertical arrangement shortens current paths and reduces the area occupied by interconnect traces, thereby minimizing parasitic resistance and inductance while maintaining fabrication flexibility across multiple dies.
Data Source
AI summary
A multi-die package structure with an embedded die embedded in a substrate, a flip chip die mounted above the substrate, and an attached die attached onto the flip chip die. The package is compact and low cost.