Multi-Die IC Package With Synchronizer Interface
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Solution Overview
Problem
The transition to smaller nanometer technologies in silicon processing leads to challenges such as pad-limited designs, incompatibility between low voltage high-speed IO logic and higher voltage interconnect technologies, and resource-intensive porting of high-speed analog interfaces, which hinder the implementation of dense digital logic and efficient integration of analog and digital circuitry.
Innovation Solution
A package comprising multiple dies with a common interface that transports both control signals and memory transactions, allowing for decoupling of analog and digital blocks, enabling different voltage and transistor gate oxide thicknesses for each die, and simplifying design, testing, and validation by using a universal communication channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size is reduced in silicon processing, then digital logic area is reduced, but analog and IO cells shrink less leading to pad-limited designs
Solution Approach 1:
The patent divides the system into multiple separate dies, each optimized for specific functions (analog, digital, IO). This segmentation allows each die to be designed independently with appropriate feature sizes, preventing the pad-limited problem from constraining digital logic density on any single die.
Solution Approach 2:
The patent transitions from a single-plane die design to a three-dimensional stacked architecture with multiple dies connected via through-silicon vias (TSVs). This dimensional change allows analog and digital circuits to be separated across different layers, increasing pad availability on each die while maintaining compact overall footprint.
2Speed
If low voltage high-speed IO logic is used, then IO performance is improved, but incompatibility with higher voltage interconnect technologies arises
Solution Approach 1:
The patent applies different voltage levels to different regions and functions within the system. Low-voltage high-speed logic is used for IO interfaces where performance is critical, while higher voltage is used for interconnects where robustness is needed. Each die and interface can be independently optimized for its specific voltage requirements.
Solution Approach 2:
The patent introduces voltage level shifters and translation circuits at the interfaces between dies with different voltage domains. These intermediary components enable communication between low-voltage IO logic and higher voltage interconnects without direct conflict, maintaining both speed and compatibility.
3Reliability
If multiple separate interfaces are used for control signals and memory transactions, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal inter-die interface that can handle multiple types of communications (control signals, memory transactions, data) through a single standardized protocol. This multi-functional interface reduces the number of separate physical connections needed while maintaining signal integrity through proper timing and synchronization mechanisms.
Solution Approach 2:
The patent combines control signals and memory transactions into a unified communication channel between dies. By merging these previously separate interfaces into one integrated protocol, the overall device complexity is reduced while signal integrity is preserved through careful protocol design and synchronization.
4Adaptability or versatility
If different transistor gate oxide thicknesses are used for different voltage requirements, then voltage compatibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent separates circuits requiring different voltage levels onto different dies or different regions of the same die. This segmentation allows each segment to be manufactured with optimized gate oxide thickness for its specific voltage requirement, while the overall system achieves multi-voltage compatibility through the segmented architecture.
Data Source
AI summary
A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.