Multi-Die Power Allocation to Rebalance Compute Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-die compute systems face performance constraints due to manufacturing variances among silicon dies, leading to differing performance levels within the same power source, resulting in inefficiencies in bulk-synchronous parallel processing where faster processors idle waiting for slower ones to finish computations.
Innovation Solution
Implementing a power management controller that performs 'energy sloshing' by distributing power between integrated circuit dies within a multi-die package, adjusting voltages to rebalance performance and power consumption, thereby reducing performance differentials and increasing overall system performance without changing the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power is distributed equally among all dies, then each die operates at its intrinsic performance level, but faster dies idle waiting for slower dies reducing overall system throughput
Solution Approach 1:
The patent applies local quality by distributing power non-uniformly across different dies based on their individual performance characteristics. Each die receives a customized power allocation that matches its intrinsic performance level, allowing faster dies to operate at higher power levels and slower dies at lower power levels, eliminating the idle time problem while maintaining overall system balance
Solution Approach 2:
The system dynamically changes the power parameter for each die based on measured performance differentials. By adjusting power levels as a controllable parameter, the system optimizes throughput by ensuring that no die becomes a bottleneck, thus reducing idle time and improving overall productivity
2Productivity
If power is increased to boost performance of slower dies, then performance differentials are reduced, but total power consumption exceeds the fixed power budget
Solution Approach 1:
The system changes the power parameter dynamically and non-uniformly across dies, allocating more power to slower dies and less to faster dies. This parameter optimization ensures that the sum of all power allocations equals the fixed power budget while maximizing overall computation throughput by eliminating performance bottlenecks
Solution Approach 2:
By applying different power levels to different dies based on their individual needs, the system achieves local optimization that translates to global throughput improvement within the fixed power budget constraint
3Manufacturing precision
If manufacturing process is changed to reduce die performance variance, then performance differentials decrease, but manufacturing complexity and cost increase
Solution Approach 1:
The system implements feedback by measuring the intrinsic performance level of each die and using this information to dynamically adjust power allocation. This feedback mechanism eliminates the need for complex manufacturing processes to ensure uniformity, as the system adapts to the actual performance characteristics of each die through software-controlled power distribution
Solution Approach 2:
Instead of changing manufacturing parameters to reduce variance, the system changes the operational power parameter to compensate for manufacturing variations. This approach maintains simple manufacturing processes while achieving performance balance through dynamic power allocation
Data Source
AI summary
A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.