Multi-Die Peak Power Circuit Grouping for NAND Load Control
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Solution Overview
Problem
Existing NAND storage systems face limitations in simultaneous peak power operations due to restricted power usage, leading to inefficient system loading and coordination challenges between memory die groups.
Innovation Solution
A peak power management system with multiple PPM groups, each containing PPM circuits with pull-up and pull-down drivers, resistors, and connected PPM pins, manages peak power operations based on electric potential, using die-to-die connections and coordinated enablement signals to regulate power usage across multiple memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are coordinated to perform peak power operations simultaneously, then power utilization efficiency is improved, but system complexity and coordination overhead increase
Solution Approach 1:
The system divides memory dies into multiple Power Management Groups (PMGs), where each PMG independently manages peak power operations for a subset of dies. This segmentation allows parallel coordination within each group while reducing the overall coordination burden compared to managing all dies in a single group.
Solution Approach 2:
The system introduces a memory controller as an intermediary that coordinates peak power operations across multiple PMGs. The controller receives power management information from each PMG and schedules operations to ensure total system power remains within the power budget, thereby managing complexity centrally while enabling distributed parallel operations.
2Reliability
If a limited number of peak power operations are performed simultaneously, then power budget constraints are satisfied, but system loading increases with unnecessary over-management
Solution Approach 1:
The system dynamically adjusts the number of simultaneous peak power operations allowed in each PMG based on real-time power budget availability. The memory controller monitors total system power consumption and flexibly allocates power headroom to different PMGs, enabling more operations when power is available and restricting them when the budget is approached.
Solution Approach 2:
The system changes the parameter of power allocation by distributing the total power budget across multiple PMGs rather than enforcing a fixed limit on individual dies. Each PMG can utilize power up to its allocated portion, and the controller adjusts these allocations dynamically, replacing static power limits with adaptive parameter management.
3Ease of operation
If memory dies are grouped into two dies per group for coordination, then peak power operations can be staggered between dies, but coordination between groups becomes problematic
Solution Approach 1:
The system makes each PMG universally applicable to any number of memory dies, rather than being limited to fixed pairs. Each PMG can manage two, three, four, or more dies depending on system configuration and power budget, allowing the same coordination mechanism to scale across different system sizes and configurations.
Solution Approach 2:
The system transitions from one-dimensional pairwise coordination to multi-dimensional group coordination. Instead of only coordinating two dies at a time, multiple PMGs can simultaneously coordinate multiple dies in parallel across different dimension groups, with the memory controller managing the higher-dimensional coordination space.
Data Source
AI summary
Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.