Multi-Die Power Rebalancing for Throughput-Limited Compute Packages

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Solution Overview

Problem

Conventional multi-die compute systems face performance constraints due to manufacturing variances among silicon dies, leading to differing performance levels within the same power source, causing slower processors to idle while waiting for faster ones to finish computations, especially in bulk-synchronous parallel applications.

Innovation Solution

Implementing a power management controller that performs 'energy sloshing' by distributing power between integrated circuit dies within a multi-die package, adjusting voltages to rebalance performance and power consumption, thereby reducing performance differentials and increasing overall system performance without changing the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional multi-die systems use uniform power distribution among silicon dies, then manufacturing simplicity is maintained, but system performance is limited by the slowest die causing idle time for faster dies

Engineering Contradiction:
Improvesystem computation throughputVSAvoididle time of faster dies
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies local quality by distributing power non-uniformly across different dies based on their individual performance characteristics. Each die receives a customized power allocation that matches its intrinsic performance level, allowing faster dies to operate at higher power levels and slower dies at lower power levels, thereby eliminating the idle time problem while maintaining manufacturing simplicity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts power distribution among dies based on real-time performance monitoring and feedback. The power management controller continuously optimizes power allocation to match actual die performance, enabling the system to adapt to manufacturing variances and maximize computation throughput by preventing faster dies from idling

Inventive Principle:
Principle #15Dynamics

2Productivity

If power is increased to match the performance of the fastest die, then computation throughput improves, but power consumption exceeds the fixed power budget

Engineering Contradiction:
Improvecomputation throughputVSAvoidtotal power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the power allocation parameter for each die individually rather than applying a uniform power level. By adjusting power parameters based on each die's intrinsic performance characteristics, the system achieves optimal computation throughput within the fixed power budget, avoiding both underutilization and overconsumption

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If uniform power allocation is used across all dies, then power management simplicity is maintained, but performance differentials between dies cause synchronization delays

Engineering Contradiction:
Improvepower management simplicityVSAvoidsynchronization waiting time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system implements feedback mechanisms where performance data from each die is monitored and used to adjust power allocation dynamically. This feedback loop maintains power management simplicity by automating the optimization process, eliminating the need for complex manual configuration while reducing synchronization delays through adaptive power distribution

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11709536B2Multi-die system performance optimization
Publication Date: 2023.07.25 ADVANCED MICRO DEVICES INC
  • US11709536B2 patent drawing
  • US11709536B2 patent drawing
  • US11709536B2 patent drawing

AI summary

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.