Multi-Die Power-State Synchronization for Blocking Latency Events
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Solution Overview
Problem
Unsynchronized power states between multiple integrated circuit dies in a multi-die architecture can cause system performance issues, such as delayed processing of access requests and memory unavailability, leading to performance loss.
Innovation Solution
A primary power manager coordinates power state transitions across multiple integrated circuit dies by issuing transition requests and acknowledgements to secondary power managers, ensuring synchronized power states through multiple synchronization points and managing latency events by broadcasting tolerance values to agents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power state transitions are managed independently on each die, then each die can optimize its own power consumption, but unsynchronized power states cause system performance issues and memory unavailability
Solution Approach 1:
The patent merges the power management functions of multiple independent dies by introducing a primary power manager that coordinates power state transitions across all dies. The primary power manager receives transition requests and distributes synchronized transition commands to secondary power managers on each die, ensuring that all dies transition to the same power state simultaneously. This coordination eliminates the performance issues caused by unsynchronized power states while maintaining the power optimization benefits of individual die control.
2Reliability
If a primary power manager coordinates power state transitions across all dies, then synchronized power states are achieved, but communication overhead and transition latency increase
Solution Approach 1:
The patent implements preliminary action by having the primary power manager broadcast transition requests to all secondary power managers before the actual power state change occurs. Each secondary power manager receives the transition request in advance, prepares its die for the transition, and acknowledges receipt to the primary power manager. This preliminary coordination allows all dies to be ready for the simultaneous transition, reducing the overall transition latency and avoiding the need for sequential transitions.
3Reliability
If multiple synchronization points are implemented during power state transitions, then power state coherence is improved, but the complexity of power management increases
Solution Approach 1:
The patent implements feedback mechanisms where secondary power managers send acknowledgment signals back to the primary power manager after receiving transition requests and completing power state transitions. The primary power manager uses this feedback to track the status of each die and ensure that all dies have successfully transitioned to the target power state. This feedback loop provides automatic verification of power state coherence without requiring complex manual monitoring, simplifying the overall management while maintaining high reliability.
Data Source
AI summary
Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.