Multi-Die Processor Interconnect Architecture for Yield and Power
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Solution Overview
Problem
Current processor designs face challenges with single large die fabrication, including increased risk of defects, limited flexibility in design, and inefficiencies in resource management, which affect performance and yield.
Innovation Solution
The implementation of a hardware processor architecture that connects multiple physically separate dies through a high-bandwidth, low-latency interconnect, allowing for shared resources, redundant functionality, and flexible design configurations, including the ability to operate with different clock frequencies and power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single large die is used for processor fabrication, then manufacturing complexity is reduced, but defect risk increases and yield decreases
Solution Approach 1:
The processor is divided into multiple separate dies, each containing specific functional units (e.g., arithmetic logic units, floating point units, graphics processors). These segmented dies are then interconnected through an interconnect structure, allowing independent fabrication and testing of each die while reducing the overall defect risk compared to a single large die.
2Reliability
If multiple separate dies are used, then defect risk is reduced, but interconnect complexity and latency increase
Solution Approach 1:
An interposer is introduced as an intermediary component between the multiple separate dies. This interposer provides a standardized interface and routing structure that simplifies the interconnection between dies, managing the complexity of multiple interconnects while enabling efficient data transfer between the segmented functional units.
3Device complexity
If all dies operate at the same clock frequency, then timing control is simplified, but power management flexibility is reduced
Solution Approach 1:
The system enables dynamic clock frequency adjustment for different dies based on their operational requirements. Each die can operate at different clock frequencies, allowing optimization of power consumption and performance for specific functional units while maintaining overall system coordination through the interconnect.
4Productivity
If resources are shared across multiple dies, then resource management efficiency improves, but coordination overhead increases
Solution Approach 1:
The interconnect structure is designed to support multiple functions including data transfer, control signal routing, and resource coordination between dies. This universal interconnect approach enables efficient resource sharing across the distributed architecture while managing coordination overhead through integrated control mechanisms.
Data Source
AI summary
Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.