Multi-Die QFN Leadframe Package for Lower Cost and Better Thermal Paths
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Solution Overview
Problem
Existing hybrid packages face challenges with high costs due to expensive package substrates and unsatisfactory thermal performance, while also aiming to reduce overall package height.
Innovation Solution
A multi-die quad-flat no-lead (QFN) hybrid package design featuring a copper leadframe carrier with flip-chip and wire-bonding leads, where two integrated circuit dies are mounted in a flip-chip manner, and a third die is stacked and connected via bond wires, encapsulated within a mold cap with exposed leads for external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a package substrate is used in hybrid package, then functionality and performance are improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and removes the expensive package substrate from the hybrid package structure, replacing it with a cost-effective leadframe carrier while maintaining the essential functionality through direct mounting of IC dies on the leadframe
Solution Approach 2:
The patent employs a leadframe carrier as a low-cost alternative to the expensive package substrate, accepting that the leadframe is a simpler, more economical structure that achieves the required function without the complexity and cost of traditional substrates
2Reliability
If a package substrate is used in hybrid package, then functionality is improved, but thermal performance deteriorates
Solution Approach 1:
The patent removes the package substrate that was causing thermal performance issues and replaces it with a leadframe carrier that provides superior thermal conduction pathways directly to the PCB, improving heat dissipation
Solution Approach 2:
The patent changes the thermal conduction parameters by using the leadframe's metal structure with high thermal conductivity, creating direct thermal paths from the IC dies through the leadframe to the PCB, thereby improving overall thermal performance
3Reliability
If traditional hybrid package structure is used, then functionality is achieved, but package height increases
Solution Approach 1:
The patent transitions from a vertical stacking arrangement to a planar layout where IC dies are mounted side-by-side on the leadframe, with bond wires routing signals overhead, thereby reducing package height while maintaining functionality
Solution Approach 2:
The patent nests the bond wires within the package structure, routing them from the IC dies to the leadframe leads in a compact configuration that minimizes vertical space requirements
Data Source
Figure 1
AI summary
A multi-die QFN hybrid package (1) includes a carrier (80) having flip-chip leads (801) and wire-bonding leads (802). A first die (10) and a second die (20) are mounted on the flip-chip leads (801), respectively, in a flip-chip manner. The first die (10) is spaced apart from the second die (20). A third die (30) is stacked over the first die (10) and the second die (20). The third die (30) is electrically connected to the wire-bonding leads (802) around the first die (10) and the second die (20) through bond wires (602). A mold cap (50) encapsulates the first die (10), the second die (20), the third die (30), the bond wires (602), and partially encapsulates the carrier (80). The flip-chip leads (801) and the wire-bonding leads (802) are exposed from a bottom mold cap surface (50b).