Multi-Die RDL Package Structure for High-Density 3D Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller, more efficient packaging techniques for semiconductor devices as demand grows for miniaturization, higher speed, greater bandwidth, and lower power consumption, with existing methods struggling to meet these requirements effectively.
Innovation Solution
The development of multi-die package structures incorporating redistribution layers (RDLs) and stacked semiconductor devices, such as logic and memory dies connected through face-to-face orientations using u-bump flip chip and metal-metal hybrid bonding, along with multiple layers of fan-out technology, to enhance connectivity and reduce physical size while maintaining high performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used, then manufacturing simplicity is maintained, but device size reduction and integration density improvement are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to three-dimensional stacked packaging architecture. Multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs) and redistribution layers (RDLs), enabling significant reduction in device footprint while increasing integration density. The stacked configuration allows signals to travel vertically through multiple layers rather than horizontally across a single plane.
Solution Approach 2:
The patent implements a nested packaging structure where multiple semiconductor dies are stacked one on top of another, with each die containing functional circuits. The dies are interconnected through TSVs that pass through intermediate layers, creating a nested arrangement where functional blocks are embedded within the vertical stack. This nesting approach maximizes the use of vertical space to achieve higher integration density.
2Quantity of substance
If feature size is continuously reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuing to reduce feature sizes in the lateral dimension, the patent exploits the vertical dimension to achieve higher integration density. Multiple dies are stacked vertically with interconnections formed through TSVs and RDLs. This dimensional transition allows increased component quantity without proportionally increasing manufacturing precision demands in the lateral plane.
Solution Approach 2:
The patent divides the integrated circuit functionality into multiple separate semiconductor dies, each fabricated using standard processes. These segmented dies are then stacked and interconnected through TSVs and RDLs. This segmentation approach allows each die to be manufactured with conventional precision requirements, while the overall system achieves higher integration density through the three-dimensional assembly.
3Volume of moving object
If stacked semiconductor devices are implemented, then physical size is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-fabricating multiple semiconductor dies with their respective circuitry before stacking. Redistribution layers are pre-formed on each die to establish the required interconnect patterns. Through-silicon vias are pre-drilled and filled during the die fabrication process. These preliminary preparations simplify the final assembly process and enable standardized manufacturing procedures for the stacked device.
Solution Approach 2:
The patent merges multiple manufacturing processes into an integrated fabrication flow. The formation of TSVs, RDLs, and die stacking are combined into a unified manufacturing sequence where processes such as copper deposition, dielectric layer formation, and via etching are performed in a coordinated manner across all dies. This merging of processes improves manufacturing efficiency despite the increased complexity of the three-dimensional structure.
Data Source
AI summary
A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.