Multi-Die RDL Interconnects Using Different Solders for Dense Packaging
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Solution Overview
Problem
Conventional approaches for achieving high-density interconnects in multi-die IC packages are limited by increased manufacturing complexity, cost, and reduced yields due to cumulative bump thickness variation and die shifting issues.
Innovation Solution
The use of microelectronic assemblies with redistribution layers (RDLs) and different solder materials for interconnects, which reduces bump thickness variation and eliminates the need for topside passivation, thereby simplifying manufacturing and increasing yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional solder interconnects are used to couple dies together, then manufacturing process is simplified, but interconnect density is limited
Solution Approach 1:
The patent divides the interconnect structure into multiple functional layers: a first solder layer for mechanical coupling, a second solder layer for electrical connection, and intermediate structures such as conductive posts and RDLs. This segmentation allows each layer to be optimized independently, achieving high interconnect density while maintaining manufacturing feasibility through specialized processes for each segment.
Solution Approach 2:
The patent transitions from conventional planar interconnects to three-dimensional stacked architectures with multiple solder layers and vertical conductive paths. By utilizing the vertical dimension and creating multi-layer interconnect structures, the patent achieves significantly higher interconnect density without proportionally increasing manufacturing complexity.
2Manufacturing precision
If conventional solder interconnects are used, then manufacturing process is simpler, but bump thickness variation accumulates
Solution Approach 1:
The patent segments the bump formation process into multiple independent stages with different solder materials deposited at different times. Each solder layer can be precisely controlled and measured independently, preventing cumulative thickness variation that occurs in conventional single-stage processes. The intermediate structures serve as reference planes for subsequent deposition steps.
Solution Approach 2:
The patent performs preliminary actions by forming conductive posts and intermediate structures before depositing the final solder layers. These preliminary structures serve as precise reference planes and templates that guide subsequent solder deposition, ensuring consistent thickness and positioning while reducing variation accumulation.
3Reliability
If conventional interconnect methods are used, then manufacturing is simpler, but die shifting and true position errors increase
Solution Approach 1:
The patent segments the coupling process into mechanical coupling (first solder layer) and electrical coupling (second solder layer) functions. The mechanical layer provides robust physical attachment that prevents die shifting, while the electrical layers provide precise positional reference. This functional segmentation improves positioning accuracy without requiring a single complex process.
Solution Approach 2:
The patent changes material parameters by using different solder materials with different properties for different functions. The first solder is optimized for mechanical strength and attachment, while subsequent solders are optimized for electrical conductivity and precision positioning. This parameter differentiation allows each layer to contribute optimally to overall positioning accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves interconnect densities comparable to or higher than conventional methods without the associated manufacturing complexities and costs, while also reducing the risk of die shifting and true position errors.
Implementation Method 1
a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer... wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.