Multi-Die Semiconductor Package Routing Automation
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Solution Overview
Problem
Electronic design automation (EDA) tools face challenges in automating the design and routing of semiconductor packages, particularly when dealing with complex register-transfer level (RTL) designs and multiple stacked dice, where optimizing hard IP blocks and mitigating electrical characteristics of vias and routes are necessary.
Innovation Solution
The implementation of EDA circuitry that selects, places, and routes cell circuitry to automate the design of semiconductor packages, including the use of multi-die vias and cell elements to mitigate electrical characteristics such as resistance and signal strength, by synthesizing RTL designs and utilizing a cell library to implement optimal configurations across multiple dice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EDA tools automate the selection, placement, and routing of cell circuitry to design semiconductor packages from RTL designs, then design automation and productivity are improved, but the complexity of optimizing electrical characteristics of vias and routes between multiple stacked dice increases
Solution Approach 1:
The patent segments the semiconductor package design into multiple independent dice, each containing specific cell circuitry. This segmentation allows the EDA tool to manage complexity by processing each die independently while maintaining overall system optimization. The via connections between dice are treated as separate optimization elements, enabling systematic management of the routing complexity across multiple stacked dice.
2Adaptability or versatility
If multiple stacked dice are used to implement complex RTL designs, then the capability to design complex semiconductor packages is improved, but the difficulty of optimizing electrical characteristics of inter-die vias and routes increases
Solution Approach 1:
The EDA tool incorporates feedback mechanisms to optimize electrical characteristics of vias and routes between stacked dice. The tool iteratively adjusts via dimensions, routing paths, and cell placements based on electrical property calculations, enabling systematic optimization of the complex inter-die connections while maintaining the versatility of multi-die package designs.
3Ease of manufacture
If cell circuitry is selected and placed automatically from a cell library to implement RTL design operations, then automation and manufacturing complexity reduction are improved, but the challenge of mitigating electrical characteristics of routes and vias increases
Solution Approach 1:
The patent employs parameter changes to optimize electrical characteristics automatically. The EDA tool adjusts via dimensions, routing trace widths, and cell placement positions as variables to achieve optimal electrical properties. This systematic parameter optimization enables the tool to mitigate electrical characteristics while maintaining automated design and reduced manufacturing complexity.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.