Multi-Die Interconnect Layout for Selectable Monolithic or External Routing

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Solution Overview

Problem

Existing integrated circuit (IC) manufacturing techniques face challenges in efficiently interconnecting multiple dies within a semiconductor wafer, particularly in achieving high-resolution connections while allowing for subsequent package-level die-to-die connections.

Innovation Solution

The implementation of redundant die-to-die routing layouts within semiconductor wafers, where a chip-level BEOL build-up structure includes die-to-die routing, inter-die routing, and through silicon vias, enabling both monolithic and external die-to-die interconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chip-level die-to-die routing is implemented within the wafer, then manufacturing precision and integration density are improved, but device complexity increases due to the need for redundant routing layouts and selection devices

Engineering Contradiction:

Improvedie-to-die connection precisionVSAvoidrouting layout complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The routing is segmented into chip-level die-to-die routing (within the wafer) and package-level die-to-die routing (external to the wafer). This segmentation allows the complex routing functionality to be divided into manageable segments that can be independently controlled and manufactured, resolving the contradiction between precision and complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The routing configuration is made dynamic through selection devices (multiplexers/demultiplexers) that can switch between chip-level and package-level routing paths. This dynamic capability allows the system to adapt to different manufacturing scenarios and defect conditions, maintaining precision while managing complexity through programmable control.

Inventive Principle:

Principle #15Dynamics

2Reliability

If redundant die-to-die routing layouts are implemented, then reliability and yield are improved, but device complexity and manufacturing cost increase

Engineering Contradiction:

Improvedie interconnection reliabilityVSAvoidrouting structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The BEOL build-up structure is designed to serve multiple functions: it provides both chip-level die-to-die routing and package-level die-to-die routing capabilities. This multi-functionality allows a single structural implementation to support redundant routing paths, improving reliability without proportionally increasing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The redundant routing paths and selection devices are built into the wafer during the chip-level manufacturing process, before the wafer is diced into individual chips. This preliminary action ensures that the reliability-enhancing redundant paths are already in place and tested, while the complexity is managed during the manufacturing phase rather than adding to the final product complexity.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If through silicon vias are included in the BEOL build-up structure, then adaptability for 3D packaging is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepackaging configuration adaptabilityVSAvoidvia formation precision

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The via structure is segmented into through silicon vias (TSVs) that can be selectively formed in different regions of the wafer. TSVs are implemented only where needed for 3D packaging applications, while other regions can use conventional routing. This segmentation allows adaptability for 3D packaging without universally increasing precision requirements across the entire wafer.

Inventive Principle:

Principle #1Segmentation

4Ease of operation

If multiple routing options are provided for die-to-die connection, then ease of operation and flexibility are improved, but device complexity increases

Engineering Contradiction:

Improverouting selection flexibilityVSAvoidrouting control complexity

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The selection devices (multiplexers/demultiplexers) are automatically controlled by control logic that selects the appropriate routing path based on the configuration and operational requirements. This self-service capability allows the system to automatically choose between chip-level and package-level routing without requiring complex external control, improving ease of operation while managing complexity through automated decision-making.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250029921A1Selectable Monolithic or External Scalable Die-to-Die Interconnection System Methodology

Publication Date: 2025.01.23 APPLE INC

AI summary

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.