Multi-die Semiconductor Structure with Intermediate Vertical Side Chip

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in integrating multiple dies within a compact form factor while maintaining high functionality and efficiency, particularly due to space constraints and thermal stresses associated with 3D stacked configurations, which limit I/O density and heat dissipation.

Innovation Solution

The implementation of multi-die semiconductor structures with intermediate vertical side chips and advanced interconnection methods such as die side pads, die backside metallization, and through silicon vias enables direct communication and increased I/O pin density, allowing for compact, high-functionality systems with enhanced heat dissipation through vertical side chip interconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor dies are stacked in 3D configuration to increase functionality, then device functionality and I/O density are improved, but thermal stress and heat dissipation become problematic

Engineering Contradiction:

Improvedevice functionalityVSAvoidthermal stress

Core Design Contradiction:

Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent transitions from conventional planar 2D die arrangement to 3D stacked configuration with vertical side chips, utilizing the vertical dimension to increase device functionality and I/O density while managing thermal stress through distributed architecture

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The semiconductor package is segmented into multiple independent dies stacked vertically, with each die contributing specific functionality. This segmentation distributes thermal load across multiple smaller units rather than concentrating heat in a single large die

Inventive Principle:

Principle #1Segmentation

2Volume of moving object

If space in semiconductor package is reduced to meet compact form factor demands, then device size is improved, but available space for additional functionality decreases

Engineering Contradiction:

Improvedevice sizeVSAvoidfunctionality

Core Design Contradiction:

Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The invention exploits the vertical dimension by stacking dies in three-dimensional configuration, allowing high functionality to be achieved within a small footprint area. The vertical side chips extend functionality without increasing the planar footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple semiconductor dies are nested vertically within a compact package structure, with each die positioned at different height levels. This nesting approach maximizes the use of vertical space to achieve high functionality in a compact form factor

Inventive Principle:

Principle #7Nested doll (Nesting)

3Strength

If conventional substrate with thick resin core layer is used, then structural support is improved, but packaging profile thickness increases

Engineering Contradiction:

Improvestructural supportVSAvoidpackaging profile

Core Design Contradiction:

StrengthVSLength of stationary object

Solution Approach 1:

The invention removes the thick resin core layer from the substrate structure, retaining only the essential functional layers. This extraction achieves a thin packaging profile while maintaining structural support through alternative design approaches

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The substrate is designed as a thin film structure without thick core layers, providing sufficient structural support for the stacked die configuration while enabling a compact packaging profile suitable for modern electronic devices

Inventive Principle:

Principle #30Flexible shells and thin films

4Adaptability or versatility

If multiple stacks of die are added to increase functionality, then device capability is improved, but space availability and structural stability worsen

Engineering Contradiction:

ImprovefunctionalityVSAvoidstructural stability

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent utilizes vertical stacking in the third dimension to add multiple die stacks without increasing planar footprint. This dimensional approach maintains structural stability by distributing weight and stress vertically through properly designed interconnection structures

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9478524B2Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Publication Date: 2016.10.25 INTEL CORP

AI summary

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.