Multi-Die Memory Interconnect Layout for Lower Signal Load
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Solution Overview
Problem
Current memory stacking techniques in multi-die packages result in increased signal load, leading to higher power consumption, larger footprint, and greater die-to-die variation, which are exacerbated by increasing stack height and clock speeds.
Innovation Solution
Implementing techniques to disconnect transmitters and electrostatic discharge components on secondary dies within the stack, using additional pads for connections, and utilizing different die types for primary and secondary dies to reduce signal load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stack height is increased to achieve higher memory density, then memory capacity increases without substantially increasing board space footprint, but the signal load on inter-die signals increases
Solution Approach 1:
The patent extracts and removes the transmitter and ESD components from secondary dies, keeping only the receiver components. This extraction eliminates the harmful signal loading effect of transmitters and ESD components on inter-die signals while preserving the necessary receive functionality, thereby reducing signal load as stack height increases
Solution Approach 2:
The patent applies different configurations to different dies in the stack: primary dies retain both transmitter and receiver components, while secondary dies have only receiver components. This local differentiation optimizes each die's function based on its role in the stack, reducing overall signal load while maintaining memory capacity
2Reliability
If the transmitter size is increased to counteract the increased signal load, then signal transmission capability is improved, but footprint usage on board space increases
Solution Approach 1:
By extracting and removing transmitter components from secondary dies, the patent eliminates the need to increase transmitter size to handle signal load, thereby avoiding the associated footprint increase while maintaining adequate signal transmission capability through the primary die transmitters
3Reliability
If the transmitter size is increased to handle the signal load, then signal transmission is improved, but current consumption increases
Solution Approach 1:
By removing transmitter components from secondary dies, the patent eliminates the current consumption associated with driving transmitters on each die in the stack. Only the primary die transmitters consume current, significantly reducing overall current consumption while maintaining signal transmission capability
4Reliability
If the transmitter size is increased to counteract signal load, then signal transmission is improved, but propagation delays increase
Solution Approach 1:
By removing transmitter and ESD components from secondary dies, the patent reduces the number of components that signals must pass through, thereby reducing propagation delays while maintaining signal transmission capability through the optimized inter-die connection architecture
5Reliability
If the transmitter size is increased to handle signal load, then signal transmission is improved, but die-to-die variation increases
Solution Approach 1:
By removing transmitter components from secondary dies, the patent reduces die-to-die variation because all secondary dies have identical receiver-only configurations. This standardization eliminates variations that would arise from different transmitter sizes or configurations across different dies
Solution Approach 2:
The patent applies a uniform receiver-only configuration to all secondary dies, creating consistency across the stack. This local standardization reduces die-to-die variation while the primary die handles all transmitter functions with a single, optimized design
Data Source
AI summary
Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.