Multi-Die Package Signal Sampling for Pad-Limited Designs
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Solution Overview
Problem
The transition to smaller nanometer technologies in silicon processing leads to challenges such as pad-limited designs, incompatibility between low voltage high-speed digital logic and higher voltage interconnect technologies, and resource-intensive porting of high-speed analogue interfaces, which hinder the dense implementation of digital logic and increase design complexity.
Innovation Solution
A package comprising multiple dies, where each die can operate with different voltage and transistor gate oxide thicknesses, allowing for decoupling of analogue and digital blocks, and using a common interface to transport both control signals and memory transactions in packets, sampled based on quality of service parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size in silicon technology is decreased to increase digital logic density, then digital logic area is reduced, but analogue and IO cells shrink less leading to pad-limited design
Solution Approach 1:
The invention divides the integrated circuit into multiple separate dies, each dedicated to specific functions (digital logic, analogue, IO). This segmentation allows each die to be optimized independently for its function without being constrained by the pad limitations affecting other functions on the same chip.
Solution Approach 2:
The invention transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture using multiple dies connected via through-silicon vias (TSVs). This vertical integration adds a new dimension, allowing digital logic dies to be stacked above IO/analogue dies, effectively increasing digital logic density without consuming additional pad area.
2Adaptability or versatility
If low voltage high speed digital logic and higher voltage interconnect technologies are integrated on the same chip, then system functionality is improved, but manufacturing compatibility is reduced due to different transistor gate oxide thicknesses
Solution Approach 1:
The invention separates low-voltage digital logic and high-voltage interconnect technologies onto different dies. Each die can be manufactured using process parameters optimized for its specific voltage requirements, eliminating the need for incompatible gate oxide thicknesses on the same chip while maintaining full system functionality.
Solution Approach 2:
The invention introduces TSVs and intermediate packaging structures as mediators between dies with different voltage characteristics. These intermediary elements enable electrical connection and signal transmission between dies manufactured with different process parameters, bridging the incompatibility gap.
3Device complexity
If multiple control signals are transported on a common interface, then device complexity is reduced, but signal sampling precision and quality of service control become more challenging
Solution Approach 1:
The invention implements dynamic signal sampling where the sampling rate and timing are adaptively adjusted based on the specific control signal being transmitted and its quality of service requirements. This dynamic approach maintains high sampling precision for critical signals while allowing less critical signals to use lower sampling rates, preserving accuracy despite multiplexing on a common interface.
Solution Approach 2:
The invention changes sampling parameters (rate, timing, trigger conditions) based on the type and priority of control signals being multiplexed on the common interface. By adapting these parameters to signal-specific quality of service requirements, the system maintains precise signal capture while reducing overall interface complexity.
Data Source
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AI summary
A package comprising a first die; a second die; an interface connecting said first die and said second die, at least one of said first and second dies comprising a memory, said interface being configured to transport both control signals and memory transactions; sampling means for sampling said control signals before transporting said control signals on said interface; and means for controlling the sampling means in dependence on at least one quality of service parameter associated with a respective control signal