Multi-Die Data-Strobe Alignment Without Balance Delay Paths
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Solution Overview
Problem
Existing cross-chip systems face issues with increased latency and power consumption due to the use of physical balance delay elements and multi-phase clock generators for synchronizing data and strobe signals, which degrade performance.
Innovation Solution
Implementing an unbalanced architecture for data and strobe paths within the dies, combined with a deskew circuit to control delay elements, ensuring the rising edge of the strobe signal aligns with the center of the data signal using control signals to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical balance delay elements and multi-phase clock generators are used to synchronize data and strobe signals, then synchronization reliability is improved, but latency increases and power consumption increases
Solution Approach 1:
The patent removes the multi-phase clock generator from the system architecture. Instead of generating multiple clock phases through complex circuitry, the invention uses a single clock signal with adjustable delay elements to achieve the same synchronization effect, thereby reducing latency and power consumption while maintaining reliability
Solution Approach 2:
The patent employs adjustable delay elements that can dynamically tune their delay characteristics based on process, voltage, and temperature variations. This dynamic adjustment allows the system to maintain synchronization reliability without requiring fixed, over-engineered delay paths, thus reducing overall latency
2Reliability
If physical balance delay elements and multi-phase clock generators are used to synchronize data and strobe signals, then synchronization reliability is improved, but power consumption increases
Solution Approach 1:
The patent eliminates the multi-phase clock generator, which is a major power consumer, from the system. By using a single clock signal with adjustable delay elements instead, the invention achieves synchronization with significantly reduced power consumption while maintaining the required reliability
Solution Approach 2:
The patent changes the approach from generating multiple clock phases (high power) to adjusting delay parameters of single-clock-based signals (low power). The adjustable delay elements modify their delay characteristics through control signals, achieving synchronization with much lower power consumption
3Adaptability or versatility
If adjustable delay elements are used within data and strobe paths, then synchronization flexibility is improved, but device complexity increases
Solution Approach 1:
The patent applies asymmetric delay adjustment by placing adjustable delay elements selectively in either the data path or the strobe path, but not both. This asymmetric approach provides sufficient synchronization flexibility to handle process variations while minimizing the added circuit complexity compared to symmetric dual-path adjustment
Data Source
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AI summary
The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.