Multi-Die Package Substrate Layout for High-Bandwidth Interconnects
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently integrating multiple dies while maintaining high bandwidth communication and space efficiency, often requiring complex circuit integration that complicates design and increases size.
Innovation Solution
A semiconductor device with multiple dies is designed using a multi-layer package substrate that includes transmission line structures with specific dimensions and configurations, such as single-ended or differential signaling structures, to establish a communication channel between dies, optimizing characteristic impedance and reducing parasitic capacitance through apertures and trace width adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuit integration is used to connect multiple dies, then communication bandwidth between dies can be maintained, but device complexity and design difficulty increase
Solution Approach 1:
The patent extracts the interconnect function from the dies themselves and places it in a separate substrate layer. The transmission lines are routed through substrate layers 204, 206, and 208, separating the computing functions (in the dies) from the communication functions (in the substrate), thereby reducing device complexity while maintaining communication bandwidth.
Solution Approach 2:
The substrate acts as an intermediary between multiple dies, providing dedicated transmission line structures that facilitate high-bandwidth communication without requiring complex integration within the dies themselves. The ground plane and dielectric layers serve as intermediaries to control impedance and reduce interference.
2Reliability
If more integrated circuitry is added between dies to improve communication, then bandwidth increases, but space efficiency decreases
Solution Approach 1:
The patent moves the interconnect structures from the horizontal plane (within die layers) to the vertical dimension (through multiple substrate layers 204, 206, 208). This allows transmission lines to route signals between dies without occupying additional horizontal space, improving space efficiency while maintaining communication bandwidth.
3Reliability
If trace width is reduced to reduce parasitic capacitance, then signal quality improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes trace dimensions and spacing parameters to achieve desired characteristic impedance values. By carefully controlling trace width, spacing between traces, and dielectric layer properties, the design achieves signal quality improvements through reduced parasitic capacitance while maintaining manufacturability through standardized parameter sets.
4Reliability
If multiple layers are added to provide transmission lines, then communication channel quality improves, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the substrate structure: transmission line routing, ground reference planes, dielectric isolation, and impedance control are all integrated into the multi-layer substrate architecture. This unified approach improves communication channel quality while avoiding the complexity of separate components for each function.
Data Source
AI summary
A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.